Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / mips / lib / cache.c

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1d14fc4..1a8c87d 100644 (file)
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <asm/cacheops.h>
 #ifdef CONFIG_MIPS_L2_CACHE
 #include <asm/cm.h>
@@ -87,7 +88,7 @@ static inline unsigned long scache_line_size(void)
 #ifdef CONFIG_MIPS_L2_CACHE
        return gd->arch.l2_line_size;
 #else
-       return 0;
+       return CONFIG_SYS_SCACHE_LINE_SIZE;
 #endif
 }
 
@@ -140,7 +141,7 @@ ops_done:
        instruction_hazard_barrier();
 }
 
-void flush_dcache_range(ulong start_addr, ulong stop)
+void __weak flush_dcache_range(ulong start_addr, ulong stop)
 {
        unsigned long lsize = dcache_line_size();
        unsigned long slsize = scache_line_size();
@@ -175,3 +176,23 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        /* ensure cache ops complete before any further memory accesses */
        sync();
 }
+
+int dcache_status(void)
+{
+       unsigned int cca = read_c0_config() & CONF_CM_CMASK;
+       return cca != CONF_CM_UNCACHED;
+}
+
+void dcache_enable(void)
+{
+       puts("Not supported!\n");
+}
+
+void dcache_disable(void)
+{
+       /* change CCA to uncached */
+       change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+
+       /* ensure the pipeline doesn't contain now-invalid instructions */
+       instruction_hazard_barrier();
+}