MIPS: Formatting clean-ups for clocksources.

[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / mips / kernel / cevt-r4k.c

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 7532392..0309aef 100644 (file)
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -23,9 +23,8 @@
  */
 
 #ifndef CONFIG_MIPS_MT_SMTC
-
 static int mips_next_event(unsigned long delta,
-                           struct clock_event_device *evt)
+                          struct clock_event_device *evt)
 {
        unsigned int cnt;
        int res;
@@ -49,7 +48,6 @@ DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 int cp0_timer_irq_installed;
 
 #ifndef CONFIG_MIPS_MT_SMTC
-
 irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 {
        const int r2 = cpu_has_mips_r2;
@@ -66,7 +64,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
                goto out;
 
        /*
-        * The same applies to performance counter interrupts.  But with the
+        * The same applies to performance counter interrupts.  But with the
         * above we now know that the reason we got here must be a timer
         * interrupt.  Being the paranoiacs we are we check anyway.
         */
@@ -119,7 +117,7 @@ int c0_compare_int_usable(void)
        unsigned int cnt;
 
        /*
-        * IP7 already pending?  Try to clear it by acking the timer.
+        * IP7 already pending?  Try to clear it by acking the timer.
         */
        if (c0_compare_int_pending()) {
                cnt = read_c0_count();
@@ -166,7 +164,6 @@ int c0_compare_int_usable(void)
 }
 
 #ifndef CONFIG_MIPS_MT_SMTC
-
 int __cpuinit r4k_clockevent_init(void)
 {
        unsigned int cpu = smp_processor_id();