dts: mtmips: add mmc related nodes for mt7628an.dtsi

[platform/kernel/u-boot.git] / arch / mips / dts / mt7628a.dtsi

diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index 8afea18..76a80c8 100644 (file)
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/clock/mt7628-clk.h>
+#include <dt-bindings/reset/mt7628-reset.h>
 
 / {
        #address-cells = <1>;
@@ -17,11 +18,6 @@
                };
        };
 
-       resetc: reset-controller {
-               compatible = "ralink,rt2880-reset";
-               #reset-cells = <1>;
-       };
-
        cpuintc: interrupt-controller {
                #address-cells = <0>;
                #interrupt-cells = <1>;
@@ -29,6 +25,14 @@
                compatible = "mti,cpu-interrupt-controller";
        };
 
+       clk48m: clk48m@0 {
+               compatible = "fixed-clock";
+
+               clock-frequency = <48000000>;
+
+               #clock-cells = <0>;
+       };
+
        palmbus@10000000 {
                compatible = "palmbus", "simple-bus";
                reg = <0x10000000 0x200000>;
@@ -57,6 +61,12 @@
                        u-boot,dm-pre-reloc;
                };
 
+               rstctrl: rstctrl@0x34 {
+                       reg = <0x34 0x4>;
+                       compatible = "mediatek,mtmips-reset";
+                       #reset-cells = <1>;
+               };
+
                pinctrl: pinctrl@60 {
                        compatible = "mediatek,mt7628-pinctrl";
                        reg = <0x3c 0x2c>, <0x1300 0x100>;
@@ -211,7 +221,7 @@
                        compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
                        reg = <0x100 0x30>;
 
-                       resets = <&resetc 8>;
+                       resets = <&rstctrl MT7628_TIMER_RST>;
                        reset-names = "wdt";
 
                        interrupt-parent = <&intc>;
@@ -225,7 +235,7 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
 
-                       resets = <&resetc 9>;
+                       resets = <&rstctrl MT7628_INT_RST>;
                        reset-names = "intc";
 
                        interrupt-parent = <&cpuintc>;
@@ -248,6 +258,9 @@
                        compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
                        reg = <0x600 0x100>;
 
+                       resets = <&rstctrl MT7628_PIO_RST>;
+                       reset-names = "pio";
+
                        interrupt-parent = <&intc>;
                        interrupts = <6>;
 
@@ -276,6 +289,10 @@
                spi0: spi@b00 {
                        compatible = "ralink,mt7621-spi";
                        reg = <0xb00 0x40>;
+
+                       resets = <&rstctrl MT7628_SPI_RST>;
+                       reset-names = "spi";
+
                        #address-cells = <1>;
                        #size-cells = <0>;
 
@@ -286,9 +303,12 @@
                        compatible = "mediatek,hsuart", "ns16550a";
                        reg = <0xc00 0x100>;
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart0_pins>;
+
                        clocks = <&clkctrl CLK_UART0>;
 
-                       resets = <&resetc 12>;
+                       resets = <&rstctrl MT7628_UART0_RST>;
                        reset-names = "uart0";
 
                        interrupt-parent = <&intc>;
@@ -301,9 +321,12 @@
                        compatible = "mediatek,hsuart", "ns16550a";
                        reg = <0xd00 0x100>;
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart1_pins>;
+
                        clocks = <&clkctrl CLK_UART1>;
 
-                       resets = <&resetc 19>;
+                       resets = <&rstctrl MT7628_UART1_RST>;
                        reset-names = "uart1";
 
                        interrupt-parent = <&intc>;
@@ -316,9 +339,12 @@
                        compatible = "mediatek,hsuart", "ns16550a";
                        reg = <0xe00 0x100>;
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_pins>;
+
                        clocks = <&clkctrl CLK_UART2>;
 
-                       resets = <&resetc 20>;
+                       resets = <&rstctrl MT7628_UART2_RST>;
                        reset-names = "uart2";
 
                        interrupt-parent = <&intc>;
@@ -328,11 +354,14 @@
                };
        };
 
-       eth@10110000 {
+       eth: eth@10110000 {
                compatible = "mediatek,mt7628-eth";
                reg = <0x10100000 0x10000
                       0x10110000 0x8000>;
 
+               resets = <&rstctrl MT7628_EPHY_RST>;
+               reset-names = "ephy";
+
                syscon = <&sysc>;
        };
 
@@ -344,8 +373,8 @@
 
                ralink,sysctl = <&sysc>;
 
-               resets = <&resetc 22 &resetc 25>;
-               reset-names = "host", "device";
+               resets = <&rstctrl MT7628_UPHY_RST>;
+               reset-names = "phy";
 
                clocks = <&clkctrl CLK_UPHY>;
                clock-names = "cg";
@@ -361,4 +390,18 @@
                interrupt-parent = <&intc>;
                interrupts = <18>;
        };
+
+       mmc: mmc@10130000 {
+               compatible = "mediatek,mt7620-mmc";
+               reg = <0x10130000 0x4000>;
+               builtin-cd = <1>;
+               r_smpl = <1>;
+
+               clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
+               clock-names = "source", "hclk";
+
+               resets = <&rstctrl MT7628_SDXC_RST>;
+
+               status = "disabled";
+       };
 };