mips: refactor disabling of caches

[platform/kernel/u-boot.git] / arch / mips / cpu / start.S

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index c3d1e64..a9f8743 100644 (file)
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -196,11 +196,10 @@ wr_done:
        mtc0    zero, CP0_COMPARE
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-       mfc0    t0, CP0_CONFIG
-       and     t0, t0, MIPS_CONF_IMPL
-       or      t0, t0, CONF_CM_UNCACHED
-       mtc0    t0, CP0_CONFIG
-       ehb
+       /* Disable caches */
+       PTR_LA  t9, mips_cache_disable
+       jalr    t9
+        nop
 #endif
 
 #ifdef CONFIG_MIPS_CM