* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
*/
addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
- swi r6, r0, 0
- lbui r10, r0, 0
+ lwi r7, r0, 0x28
+ swi r6, r0, 0x28 /* used first unused MB vector */
+ lbui r10, r0, 0x28 /* used first unused MB vector */
+ swi r7, r0, 0x28
/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
addik r6, r0, CONFIG_SYS_RESET_ADDRESS
sw r6, r1, r0
- lhu r7, r1, r0
- shi r7, r0, 0x2
- shi r6, r0, 0x6
-/*
- * Copy U-Boot code to CONFIG_SYS_TEXT_BASE
- * solve problem with sbrk_base
- */
-#if (CONFIG_SYS_RESET_ADDRESS != CONFIG_SYS_TEXT_BASE)
- addi r4, r0, __end
- addi r5, r0, __text_start
- rsub r4, r5, r4 /* size = __end - __text_start */
- addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */
- addi r7, r0, 0 /* counter */
-4:
- lw r8, r6, r7
- sw r8, r5, r7
- addi r7, r7, 0x4
- cmp r8, r4, r7
- blti r8, 4b
-#endif
+ lhu r7, r1, r10
+ rsubi r8, r10, 0x2
+ sh r7, r0, r8
+ rsubi r8, r10, 0x6
+ sh r6, r0, r8
#endif
#ifdef CONFIG_SYS_USR_EXCEP
sh r6, r0, r8
#endif
-#ifdef CONFIG_SYS_INTC_0
/* interrupt_handler */
swi r2, r0, 0x10 /* interrupt - imm opcode */
swi r3, r0, 0x14 /* interrupt - brai opcode */
sh r7, r0, r8
rsubi r8, r10, 0x16
sh r6, r0, r8
-#endif
/* hardware exception */
swi r2, r0, 0x20 /* hardware exception - imm opcode */
rsubi r8, r10, 0x26
sh r6, r0, r8
+ /* Flush cache before enable cache */
+ addik r5, r0, 0
+ addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush: bralid r15, flush_cache
+ nop
+
/* enable instruction and data cache */
mfs r12, rmsr
ori r12, r12, 0xa0
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
- brai board_init
+ brai board_init_f
1: bri 1b
/*