Convert CONFIG_SPL_STACK to Kconfig

[platform/kernel/u-boot.git] / arch / microblaze / cpu / start.S

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 9479737..25e9968 100644 (file)
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -15,11 +15,11 @@
 _start:
        mts     rmsr, r0        /* disable cache */
 
-       addi    r8, r0, __end
+       addi    r8, r0, _end
        mts     rslr, r8
 
 #if defined(CONFIG_SPL_BUILD)
-       addi    r1, r0, CONFIG_SPL_STACK_ADDR
+       addi    r1, r0, CONFIG_SPL_STACK
 #else
        addi    r1, r0, CONFIG_SYS_INIT_SP_OFFSET
 #endif
@@ -105,15 +105,17 @@ clear_bss:
  * r10: Stores little/big endian offset for vectors
  * r2: Stores imm opcode
  * r3: Stores brai opcode
+ * r4: Stores the vector base address
  */
 __setup_exceptions:
-       addik   r1, r1, -28
+       addik   r1, r1, -32
        swi     r2, r1, 4
        swi     r3, r1, 8
-       swi     r6, r1, 12
-       swi     r7, r1, 16
-       swi     r8, r1, 20
-       swi     r10, r1, 24
+       swi     r4, r1, 12
+       swi     r6, r1, 16
+       swi     r7, r1, 20
+       swi     r8, r1, 24
+       swi     r10, r1, 28
 
        /* Find-out if u-boot is running on BIG/LITTLE endian platform
         * There are some steps which is necessary to keep in mind:
@@ -125,33 +127,32 @@ __setup_exceptions:
         * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
         */
        addik   r6, r0, 0x2 /* BIG/LITTLE endian offset */
-       lwi     r7, r0, 0x28
-       swi     r6, r0, 0x28 /* used first unused MB vector */
-       lbui    r10, r0, 0x28 /* used first unused MB vector */
-       swi     r7, r0, 0x28
+       sw      r6, r1, r0
+       lbu     r10, r1, r0
 
        /* add opcode instruction for 32bit jump - 2 instruction imm & brai */
        addi    r2, r0, 0xb0000000      /* hex b000 opcode imm */
        addi    r3, r0, 0xb8080000      /* hew b808 opcode brai */
 
-#ifdef CONFIG_SYS_RESET_ADDRESS
+       /* Store the vector base address in r4 */
+       addi    r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
+
        /* reset address */
-       swi     r2, r0, 0x0     /* reset address - imm opcode */
-       swi     r3, r0, 0x4     /* reset address - brai opcode */
+       swi     r2, r4, 0x0     /* reset address - imm opcode */
+       swi     r3, r4, 0x4     /* reset address - brai opcode */
 
-       addik   r6, r0, CONFIG_SYS_RESET_ADDRESS
+       addik   r6, r0, CONFIG_SYS_TEXT_BASE
        sw      r6, r1, r0
        lhu     r7, r1, r10
        rsubi   r8, r10, 0x2
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0x6
-       sh      r6, r0, r8
-#endif
+       sh      r6, r4, r8
 
-#ifdef CONFIG_SYS_USR_EXCEP
+#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
        /* user_vector_exception */
-       swi     r2, r0, 0x8     /* user vector exception - imm opcode */
-       swi     r3, r0, 0xC     /* user vector exception - brai opcode */
+       swi     r2, r4, 0x8     /* user vector exception - imm opcode */
+       swi     r3, r4, 0xC     /* user vector exception - brai opcode */
 
        addik   r6, r5, _exception_handler
        sw      r6, r1, r0
@@ -177,42 +178,43 @@ __setup_exceptions:
         */
        lhu     r7, r1, r10
        rsubi   r8, r10, 0xa
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0xe
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 #endif
 
        /* interrupt_handler */
-       swi     r2, r0, 0x10    /* interrupt - imm opcode */
-       swi     r3, r0, 0x14    /* interrupt - brai opcode */
+       swi     r2, r4, 0x10    /* interrupt - imm opcode */
+       swi     r3, r4, 0x14    /* interrupt - brai opcode */
 
        addik   r6, r5, _interrupt_handler
        sw      r6, r1, r0
        lhu     r7, r1, r10
        rsubi   r8, r10, 0x12
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0x16
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 
        /* hardware exception */
-       swi     r2, r0, 0x20    /* hardware exception - imm opcode */
-       swi     r3, r0, 0x24    /* hardware exception - brai opcode */
+       swi     r2, r4, 0x20    /* hardware exception - imm opcode */
+       swi     r3, r4, 0x24    /* hardware exception - brai opcode */
 
        addik   r6, r5, _hw_exception_handler
        sw      r6, r1, r0
        lhu     r7, r1, r10
        rsubi   r8, r10, 0x22
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0x26
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 
-       lwi     r10, r1, 24
-       lwi     r8, r1, 20
-       lwi     r7, r1, 16
-       lwi     r6, r1, 12
+       lwi     r10, r1, 28
+       lwi     r8, r1, 24
+       lwi     r7, r1, 20
+       lwi     r6, r1, 16
+       lwi     r4, r1, 12
        lwi     r3, r1, 8
        lwi     r2, r1, 4
-       addik   r1, r1, 28
+       addik   r1, r1, 32
 
        rtsd    r15, 8
        or      r0, r0, r0
@@ -270,7 +272,7 @@ relocate_code:
        add     r23, r0, r7 /* Move reloc addr to r23 */
        /* Relocate text and data - r12 temp value */
        addi    r21, r0, _start
-       addi    r22, r0, __end - 4 /* Include BSS too */
+       addi    r22, r0, _end - 4 /* Include BSS too */
 
        rsub    r6, r21, r22
        or      r5, r0, r0