ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x

[platform/kernel/u-boot.git] / arch / m68k / cpu / mcf547x_8x / pci.c

diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c
index f867dc1..1a81e3f 100644 (file)
--- a/arch/m68k/cpu/mcf547x_8x/pci.c
+++ b/arch/m68k/cpu/mcf547x_8x/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -88,53 +88,56 @@ int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
 
 void pci_mcf547x_8x_init(struct pci_controller *hose)
 {
-       volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       pci_t *pci = (pci_t *) MMAP_PCI;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Port configuration */
-       gpio->par_pcibg =
-           GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
-           GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
-           GPIO_PAR_PCIBG_PCIBG4(3);
-       gpio->par_pcibr =
-           GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
-           GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
-           GPIO_PAR_PCIBR_PCIBR4(3);
+       out_be16(&gpio->par_pcibg,
+               GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
+               GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
+               GPIO_PAR_PCIBG_PCIBG4(3));
+       out_be16(&gpio->par_pcibr,
+               GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
+               GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
+               GPIO_PAR_PCIBR_PCIBR4(3));
 
        /* Assert reset bit */
-       pci->gscr |= PCI_GSCR_PR;
+       setbits_be32(&pci->gscr, PCI_GSCR_PR);
 
-       pci->tcr1 = PCI_TCR1_P;
+       out_be32(&pci->tcr1, PCI_TCR1_P);
 
        /* Initiator windows */
-       pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
-       pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
-       pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
+       out_be32(&pci->iw0btar,
+               CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+       out_be32(&pci->iw1btar,
+               CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+       out_be32(&pci->iw2btar,
+               CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
 
-       pci->iwcr =
-           PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
-           PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+       out_be32(&pci->iwcr,
+               PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+               PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
 
-       pci->icr = 0;
+       out_be32(&pci->icr, 0);
 
        /* Enable bus master and mem access */
-       pci->scr = PCI_SCR_B | PCI_SCR_M;
+       out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
 
        /* Cache line size and master latency */
-       pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
-       pci->cr2 = 0;
+       out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
+       out_be32(&pci->cr2, 0);
 
 #ifdef CONFIG_SYS_PCI_BAR0
-       pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
-       pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
+       out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+       out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
 #endif
 #ifdef CONFIG_SYS_PCI_BAR1
-       pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
-       pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
+       out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+       out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
 #endif
 
        /* Deassert reset bit */
-       pci->gscr &= ~PCI_GSCR_PR;
+       clrbits_be32(&pci->gscr, PCI_GSCR_PR);
        udelay(1000);
 
        /* Enable PCI bus master support */