Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

[profile/ivi/kernel-adaptation-intel-automotive.git] / arch / ia64 / sn / pci / tioce_provider.c

diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
index 84b72b2..999f14f 100644 (file)
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -41,7 +41,7 @@
  *     } else
  *             do desired mmr access
  *
- * According to hw, we can use reads instead of writes to the above addres
+ * According to hw, we can use reads instead of writes to the above address
  *
  * Note this WAR can only to be used for accessing internal MMR's in the
  * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff.  This includes the
@@ -752,13 +752,13 @@ tioce_kern_init(struct tioce_common *tioce_common)
         * Determine the secondary bus number of the port2 logical PPB.
         * This is used to decide whether a given pci device resides on
         * port1 or port2.  Note:  We don't have enough plumbing set up
-        * here to use pci_read_config_xxx() so use the raw_pci_ops vector.
+        * here to use pci_read_config_xxx() so use raw_pci_read().
         */
 
        seg = tioce_common->ce_pcibus.bs_persist_segment;
        bus = tioce_common->ce_pcibus.bs_persist_busnum;
 
-       raw_pci_ops->read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
+       raw_pci_read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp);
        tioce_kern->ce_port1_secondary = (u8) tmp;
 
        /*
@@ -799,11 +799,11 @@ tioce_kern_init(struct tioce_common *tioce_common)
 
                /* mem base/limit */
 
-               raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
+               raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
                                  PCI_MEMORY_BASE, 2, &tmp);
                base = (u64)tmp << 16;
 
-               raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
+               raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
                                  PCI_MEMORY_LIMIT, 2, &tmp);
                limit = (u64)tmp << 16;
                limit |= 0xfffffUL;
@@ -817,21 +817,21 @@ tioce_kern_init(struct tioce_common *tioce_common)
                 * attributes.
                 */
 
-               raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
+               raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
                                  PCI_PREF_MEMORY_BASE, 2, &tmp);
                base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
 
-               raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
+               raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
                                  PCI_PREF_BASE_UPPER32, 4, &tmp);
                base |= (u64)tmp << 32;
 
-               raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
+               raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
                                  PCI_PREF_MEMORY_LIMIT, 2, &tmp);
 
                limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16;
                limit |= 0xfffffUL;
 
-               raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0),
+               raw_pci_read(seg, bus, PCI_DEVFN(dev, 0),
                                  PCI_PREF_LIMIT_UPPER32, 4, &tmp);
                limit |= (u64)tmp << 32;
 
@@ -1034,6 +1034,7 @@ tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                       tioce_common->ce_pcibus.bs_persist_segment,
                       tioce_common->ce_pcibus.bs_persist_busnum);
 
+       sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
        return tioce_common;
 }