arm64: ensure completion of TLB invalidatation

[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / arm64 / mm / proc.S

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index b1b31bb..0f7fec5 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -111,12 +111,12 @@ ENTRY(__cpu_setup)
        bl      __flush_dcache_all
        mov     lr, x28
        ic      iallu                           // I+BTB cache invalidate
+       tlbi    vmalle1is                       // invalidate I + D TLBs
        dsb     sy
 
        mov     x0, #3 << 20
        msr     cpacr_el1, x0                   // Enable FP/ASIMD
        msr     mdscr_el1, xzr                  // Reset mdscr_el1
-       tlbi    vmalle1is                       // invalidate I + D TLBs
        /*
         * Memory region attributes for LPAE:
         *
@@ -162,9 +162,9 @@ ENDPROC(__cpu_setup)
         *       CE0      XWHW CZ     ME TEEA S
         * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
         * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
-        * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
+        * .... .1.. .... 01.1 11.1 ..01 0001 1101 < software settings
         */
        .type   crval, #object
 crval:
-       .word   0x030802e2                      // clear
+       .word   0x000802e2                      // clear
        .word   0x0405d11d                      // set