Merge branch 'for-next/alternatives' into for-next/core
[platform/kernel/linux-starfive.git] / arch / arm64 / include / asm / assembler.h
index d851e27..e5957a5 100644 (file)
@@ -384,8 +384,8 @@ alternative_cb_end
        .macro  tcr_compute_pa_size, tcr, pos, tmp0, tmp1
        mrs     \tmp0, ID_AA64MMFR0_EL1
        // Narrow PARange to fit the PS field in TCR_ELx
-       ubfx    \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
-       mov     \tmp1, #ID_AA64MMFR0_PARANGE_MAX
+       ubfx    \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3
+       mov     \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX
        cmp     \tmp0, \tmp1
        csel    \tmp0, \tmp1, \tmp0, hi
        bfi     \tcr, \tmp0, \pos, #3
@@ -512,7 +512,7 @@ alternative_endif
  */
        .macro  reset_pmuserenr_el0, tmpreg
        mrs     \tmpreg, id_aa64dfr0_el1
-       sbfx    \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
+       sbfx    \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
        cmp     \tmpreg, #1                     // Skip if no PMU present
        b.lt    9000f
        msr     pmuserenr_el0, xzr              // Disable PMU access from EL0
@@ -524,7 +524,7 @@ alternative_endif
  */
        .macro  reset_amuserenr_el0, tmpreg
        mrs     \tmpreg, id_aa64pfr0_el1        // Check ID_AA64PFR0_EL1
-       ubfx    \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4
+       ubfx    \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
        cbz     \tmpreg, .Lskip_\@              // Skip if no AMU present
        msr_s   SYS_AMUSERENR_EL0, xzr          // Disable AMU access from EL0
 .Lskip_\@:
@@ -612,7 +612,7 @@ alternative_endif
        .macro  offset_ttbr1, ttbr, tmp
 #ifdef CONFIG_ARM64_VA_BITS_52
        mrs_s   \tmp, SYS_ID_AA64MMFR2_EL1
-       and     \tmp, \tmp, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
+       and     \tmp, \tmp, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)
        cbnz    \tmp, .Lskipoffs_\@
        orr     \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
 .Lskipoffs_\@ :