arm64: dts: rockchip: Add NanoPC T6 PCIe e-key support

[platform/kernel/linux-starfive.git] / arch / arm64 / boot / dts / rockchip / rk3588-nanopc-t6.dts

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index 0bd80e5..97af4f9 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -137,6 +137,18 @@
                vin-supply = <&vcc5v0_sys>;
        };
 
+       vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pcie_m2_1_pwren>;
+               regulator-name = "vcc3v3_pcie2x1l0";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vcc5v0_sys>;
+       };
+
        vcc3v3_pcie30: vcc3v3-pcie30-regulator {
                compatible = "regulator-fixed";
                enable-active-high;
@@ -421,6 +433,14 @@
        status = "okay";
 };
 
+&pcie2x1l1 {
+       reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+       vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_1_rst>;
+       status = "okay";
+};
+
 &pcie2x1l2 {
        reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
        vpcie3v3-supply = <&vcc_3v3_pcie20>;
@@ -467,6 +487,10 @@
                        rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
+               pcie2_1_rst: pcie2-1-rst {
+                       rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
                pcie2_2_rst: pcie2-2-rst {
                        rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
                };
@@ -474,6 +498,10 @@
                pcie_m2_0_pwren: pcie-m20-pwren {
                        rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
+
+               pcie_m2_1_pwren: pcie-m21-pwren {
+                       rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
        };
 
        usb {