Merge tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[platform/kernel/linux-starfive.git] / arch / arm64 / boot / dts / qcom / sm8250.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index d12e4cb..6f6129b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -13,7 +13,6 @@
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sm8250.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
-#include <dt-bindings/power/qcom-aoss-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,apr.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -273,13 +272,6 @@
                reg = <0x0 0x80000000 0x0 0x0>;
        };
 
-       mmcx_reg: mmcx-reg {
-               compatible = "regulator-fixed-domain";
-               power-domains = <&rpmhpd SM8250_MMCX>;
-               required-opps = <&rpmhpd_opp_low_svs>;
-               regulator-name = "MMCX";
-       };
-
        pmu {
                compatible = "arm,armv8-pmuv3";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -1463,7 +1455,7 @@
 
                        status = "disabled";
 
-                       pcie0_lane: lanes@1c06200 {
+                       pcie0_lane: phy@1c06200 {
                                reg = <0 0x1c06200 0 0x170>, /* tx */
                                      <0 0x1c06400 0 0x200>, /* rx */
                                      <0 0x1c06800 0 0x1f0>, /* pcs */
@@ -1567,7 +1559,7 @@
 
                        status = "disabled";
 
-                       pcie1_lane: lanes@1c0e200 {
+                       pcie1_lane: phy@1c0e200 {
                                reg = <0 0x1c0e200 0 0x170>, /* tx0 */
                                      <0 0x1c0e400 0 0x200>, /* rx0 */
                                      <0 0x1c0ea00 0 0x1f0>, /* pcs */
@@ -1673,7 +1665,7 @@
 
                        status = "disabled";
 
-                       pcie2_lane: lanes@1c16200 {
+                       pcie2_lane: phy@1c16200 {
                                reg = <0 0x1c16200 0 0x170>, /* tx0 */
                                      <0 0x1c16400 0 0x200>, /* rx0 */
                                      <0 0x1c16a00 0 0x1f0>, /* pcs */
@@ -1750,7 +1742,7 @@
                        reset-names = "ufsphy";
                        status = "disabled";
 
-                       ufs_mem_phy_lanes: lanes@1d87400 {
+                       ufs_mem_phy_lanes: phy@1d87400 {
                                reg = <0 0x01d87400 0 0x108>,
                                      <0 0x01d87600 0 0x1e0>,
                                      <0 0x01d87c00 0 0x1dc>,
@@ -2088,13 +2080,14 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
-                                       <&rpmhpd SM8250_LCX>,
+                       power-domains = <&rpmhpd SM8250_LCX>,
                                        <&rpmhpd SM8250_LMX>;
-                       power-domain-names = "load_state", "lcx", "lmx";
+                       power-domain-names = "lcx", "lmx";
 
                        memory-region = <&slpi_mem>;
 
+                       qcom,qmp = <&aoss_qmp>;
+
                        qcom,smem-states = <&smp2p_slpi_out 0>;
                        qcom,smem-state-names = "stop";
 
@@ -2154,12 +2147,12 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
-                                       <&rpmhpd SM8250_CX>;
-                       power-domain-names = "load_state", "cx";
+                       power-domains = <&rpmhpd SM8250_CX>;
 
                        memory-region = <&cdsp_mem>;
 
+                       qcom,qmp = <&aoss_qmp>;
+
                        qcom,smem-states = <&smp2p_cdsp_out 0>;
                        qcom,smem-state-names = "stop";
 
@@ -2330,7 +2323,7 @@
                                 <&gcc GCC_USB3_PHY_SEC_BCR>;
                        reset-names = "phy", "common";
 
-                       usb_2_ssphy: lanes@88eb200 {
+                       usb_2_ssphy: phy@88eb200 {
                                reg = <0 0x088eb200 0 0x200>,
                                      <0 0x088eb400 0 0x200>,
                                      <0 0x088eb800 0 0x800>;
@@ -2571,7 +2564,8 @@
                        clocks = <&gcc GCC_VIDEO_AHB_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK_A>;
-                       mmcx-supply = <&mmcx_reg>;
+                       power-domains = <&rpmhpd SM8250_MMCX>;
+                       required-opps = <&rpmhpd_opp_low_svs>;
                        clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
@@ -2846,7 +2840,8 @@
                dispcc: clock-controller@af00000 {
                        compatible = "qcom,sm8250-dispcc";
                        reg = <0 0x0af00000 0 0x10000>;
-                       mmcx-supply = <&mmcx_reg>;
+                       power-domains = <&rpmhpd SM8250_MMCX>;
+                       required-opps = <&rpmhpd_opp_low_svs>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&dsi0_phy 0>,
                                 <&dsi0_phy 1>,
@@ -2900,7 +2895,7 @@
 
                aoss_qmp: power-controller@c300000 {
                        compatible = "qcom,sm8250-aoss-qmp";
-                       reg = <0 0x0c300000 0 0x100000>;
+                       reg = <0 0x0c300000 0 0x400>;
                        interrupts-extended = <&ipcc IPCC_CLIENT_AOP
                                                     IPCC_MPROC_SIGNAL_GLINK_QMP
                                                     IRQ_TYPE_EDGE_RISING>;
@@ -2908,7 +2903,11 @@
                                        IPCC_MPROC_SIGNAL_GLINK_QMP>;
 
                        #clock-cells = <0>;
-                       #power-domain-cells = <1>;
+               };
+
+               sram@c3f0000 {
+                       compatible = "qcom,rpmh-stats";
+                       reg = <0 0x0c3f0000 0 0x400>;
                };
 
                spmi_bus: spmi@c440000 {
@@ -3825,13 +3824,14 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
-                                       <&rpmhpd SM8250_LCX>,
+                       power-domains = <&rpmhpd SM8250_LCX>,
                                        <&rpmhpd SM8250_LMX>;
-                       power-domain-names = "load_state", "lcx", "lmx";
+                       power-domain-names = "lcx", "lmx";
 
                        memory-region = <&adsp_mem>;
 
+                       qcom,qmp = <&aoss_qmp>;
+
                        qcom,smem-states = <&smp2p_adsp_out 0>;
                        qcom,smem-state-names = "stop";