Merge tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

[platform/kernel/linux-rpi.git] / arch / arm64 / boot / dts / qcom / sdm845.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 860d5c2..8eb5a31 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
@@ -1761,6 +1762,8 @@
 
                ipa: ipa@1e40000 {
                        compatible = "qcom,sdm845-ipa";
+
+                       iommus = <&apps_smmu 0x720 0x3>;
                        reg = <0 0x1e40000 0 0x7000>,
                              <0 0x1e47000 0 0x2000>,
                              <0 0x1e04000 0 0x2c000>;
@@ -1813,6 +1816,42 @@
                        gpio-ranges = <&tlmm 0 0 150>;
                        wakeup-parent = <&pdc_intc>;
 
+                       cci0_default: cci0-default {
+                               /* SDA, SCL */
+                               pins = "gpio17", "gpio18";
+                               function = "cci_i2c";
+
+                               bias-pull-up;
+                               drive-strength = <2>; /* 2 mA */
+                       };
+
+                       cci0_sleep: cci0-sleep {
+                               /* SDA, SCL */
+                               pins = "gpio17", "gpio18";
+                               function = "cci_i2c";
+
+                               drive-strength = <2>; /* 2 mA */
+                               bias-pull-down;
+                       };
+
+                       cci1_default: cci1-default {
+                               /* SDA, SCL */
+                               pins = "gpio19", "gpio20";
+                               function = "cci_i2c";
+
+                               bias-pull-up;
+                               drive-strength = <2>; /* 2 mA */
+                       };
+
+                       cci1_sleep: cci1-sleep {
+                               /* SDA, SCL */
+                               pins = "gpio19", "gpio20";
+                               function = "cci_i2c";
+
+                               drive-strength = <2>; /* 2 mA */
+                               bias-pull-down;
+                       };
+
                        qspi_clk: qspi-clk {
                                pinmux {
                                        pins = "gpio95";
@@ -2970,7 +3009,7 @@
                };
 
                usb_1_hsphy: phy@88e2000 {
-                       compatible = "qcom,sdm845-qusb2-phy";
+                       compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
                        reg = <0 0x088e2000 0 0x400>;
                        status = "disabled";
                        #phy-cells = <0>;
@@ -2985,7 +3024,7 @@
                };
 
                usb_2_hsphy: phy@88e3000 {
-                       compatible = "qcom,sdm845-qusb2-phy";
+                       compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
                        reg = <0 0x088e3000 0 0x400>;
                        status = "disabled";
                        #phy-cells = <0>;
@@ -3202,6 +3241,61 @@
                        #reset-cells = <1>;
                };
 
+               cci: cci@ac4a000 {
+                       compatible = "qcom,sdm845-cci";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       reg = <0 0x0ac4a000 0 0x4000>;
+                       interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+                       power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+                       clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+                               <&clock_camcc CAM_CC_SOC_AHB_CLK>,
+                               <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+                               <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+                               <&clock_camcc CAM_CC_CCI_CLK>,
+                               <&clock_camcc CAM_CC_CCI_CLK_SRC>;
+                       clock-names = "camnoc_axi",
+                               "soc_ahb",
+                               "slow_ahb_src",
+                               "cpas_ahb",
+                               "cci",
+                               "cci_src";
+
+                       assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+                               <&clock_camcc CAM_CC_CCI_CLK>;
+                       assigned-clock-rates = <80000000>, <37500000>;
+
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&cci0_default &cci1_default>;
+                       pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+
+                       status = "disabled";
+
+                       cci_i2c0: i2c-bus@0 {
+                               reg = <0>;
+                               clock-frequency = <1000000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       cci_i2c1: i2c-bus@1 {
+                               reg = <1>;
+                               clock-frequency = <1000000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
+               clock_camcc: clock-controller@ad00000 {
+                       compatible = "qcom,sdm845-camcc";
+                       reg = <0 0x0ad00000 0 0x10000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                mdss: mdss@ae00000 {
                        compatible = "qcom,sdm845-mdss";
                        reg = <0 0x0ae00000 0 0x1000>;