#size-cells = <2>;
ranges;
- mba_region: mba@91500000 {
- reg = <0x0 0x91500000 0x0 0x200000>;
+ hyp_mem: memory@85800000 {
+ reg = <0x0 0x85800000 0x0 0x600000>;
no-map;
};
- slpi_region: slpi@90b00000 {
- reg = <0x0 0x90b00000 0x0 0xa00000>;
+ xbl_mem: memory@85e00000 {
+ reg = <0x0 0x85e00000 0x0 0x200000>;
no-map;
};
- venus_region: venus@90400000 {
- reg = <0x0 0x90400000 0x0 0x700000>;
+ smem_mem: smem-mem@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
- adsp_region: adsp@8ea00000 {
- reg = <0x0 0x8ea00000 0x0 0x1a00000>;
+ tz_mem: memory@86200000 {
+ reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
- mpss_region: mpss@88800000 {
- reg = <0x0 0x88800000 0x0 0x6200000>;
+ rmtfs_mem: rmtfs {
+ compatible = "qcom,rmtfs-mem";
+
+ size = <0x0 0x200000>;
+ alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
};
- smem_mem: smem-mem@86000000 {
- reg = <0x0 0x86000000 0x0 0x200000>;
+ mpss_mem: mpss@88800000 {
+ reg = <0x0 0x88800000 0x0 0x6200000>;
no-map;
};
- memory@85800000 {
- reg = <0x0 0x85800000 0x0 0x800000>;
+ adsp_mem: adsp@8ea00000 {
+ reg = <0x0 0x8ea00000 0x0 0x1b00000>;
no-map;
};
- memory@86200000 {
- reg = <0x0 0x86200000 0x0 0x2600000>;
+ slpi_mem: slpi@90500000 {
+ reg = <0x0 0x90500000 0x0 0xa00000>;
no-map;
};
- rmtfs@86700000 {
- compatible = "qcom,rmtfs-mem";
-
- size = <0x0 0x200000>;
- alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+ gpu_mem: gpu@90f00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90f00000 0x0 0x100000>;
no-map;
+ };
- qcom,client-id = <1>;
- qcom,vmid = <15>;
+ venus_mem: venus@91000000 {
+ reg = <0x0 0x91000000 0x0 0x500000>;
+ no-map;
};
- zap_shader_region: gpu@8f200000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x90b00000 0x0 0xa00000>;
+ mba_mem: mba@91500000 {
+ reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
};
qcom,glink-channels = "rpm_requests";
rpmcc: qcom,rpmcc {
- compatible = "qcom,rpmcc-msm8996";
+ compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
#clock-cells = <1>;
};
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
- smp2p_adsp_out: master-kernel {
+ adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
- smp2p_adsp_in: slave-kernel {
+ adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
};
};
- smp2p-modem {
+ smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
- modem_smp2p_out: master-kernel {
+ mpss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
- modem_smp2p_in: slave-kernel {
+ mpss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
- smp2p_slpi_in: slave-kernel {
+ slpi_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ slpi_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
+
interrupt-controller;
#interrupt-cells = <2>;
};
-
- smp2p_slpi_out: master-kernel {
- qcom,entry-name = "master-kernel";
- #qcom,smem-state-cells = <1>;
- };
};
soc: soc {
#thermal-sensor-cells = <1>;
};
- cryptobam: dma@644000 {
+ cryptobam: dma-controller@644000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00644000 0x24000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <4>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
"hdcp_physical";
interrupt-parent = <&mdss>;
- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <8>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
};
zap-shader {
- memory-region = <&zap_shader_region>;
+ memory-region = <&gpu_mem>;
};
};
ranges;
pcie0: pcie@600000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ compatible = "qcom,pcie-msm8996";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
};
pcie1: pcie@608000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ compatible = "qcom,pcie-msm8996";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
};
pcie2: pcie@610000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ compatible = "qcom,pcie-msm8996";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
};
ufshc: ufshc@624000 {
- compatible = "qcom,ufshc";
+ compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
- memory-region = <&venus_region>;
+ memory-region = <&venus_mem>;
status = "disabled";
video-decoder {
clock-names = "iface", "bus";
};
+ slpi_pil: remoteproc@1c00000 {
+ compatible = "qcom,msm8996-slpi-pil";
+ reg = <0x01c00000 0x4000>;
+
+ interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&xo_board>,
+ <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
+ clock-names = "xo", "aggre2";
+
+ memory-region = <&slpi_mem>;
+
+ qcom,smem-states = <&slpi_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ power-domains = <&rpmpd MSM8996_VDDSSCX>;
+ power-domain-names = "ssc_cx";
+
+ status = "disabled";
+
+ smd-edge {
+ interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
+
+ label = "dsps";
+ mboxes = <&apcs_glb 25>;
+ qcom,smd-edge = <3>;
+ qcom,remote-pid = <3>;
+ };
+ };
+
+ mss_pil: remoteproc@2080000 {
+ compatible = "qcom,msm8996-mss-pil";
+ reg = <0x2080000 0x100>,
+ <0x2180000 0x020>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&xo_board>,
+ <&gcc GCC_MSS_GPLL0_DIV_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
+ <&rpmcc RPM_SMD_PCNOC_CLK>,
+ <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
+ "snoc_axi", "mnoc_axi", "pnoc", "qdss";
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ power-domains = <&rpmpd MSM8996_VDDCX>,
+ <&rpmpd MSM8996_VDDMX>;
+ power-domain-names = "cx", "mx";
+
+ qcom,smem-states = <&mpss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
+
+ status = "disabled";
+
+ mba {
+ memory-region = <&mba_mem>;
+ };
+
+ mpss {
+ memory-region = <&mpss_mem>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+
+ label = "mpss";
+ mboxes = <&apcs_glb 12>;
+ qcom,smd-edge = <0>;
+ qcom,remote-pid = <1>;
+ };
+ };
+
stm@3002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x3002000 0x1000>,
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>;
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b7000 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>;
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c5_default>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75ba000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c6_default>;
pinctrl-1 = <&blsp2_i2c6_sleep>;
reg = <0x09300000 0x80000>;
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
clock-names = "xo";
- memory-region = <&adsp_region>;
+ memory-region = <&adsp_mem>;
- qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
power-domains = <&rpmpd MSM8996_VDDCX>;
projects / platform / kernel / linux-starfive.git / blobdiff