arm64: dts: mediatek: mt8186: fix clock names for power domains

[platform/kernel/linux-starfive.git] / arch / arm64 / boot / dts / mediatek / mt8186.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index f04ae70..8598aa1 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -924,7 +924,8 @@
                                        reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
                                        clocks = <&topckgen CLK_TOP_SENINF>,
                                                 <&topckgen CLK_TOP_SENINF1>;
-                                       clock-names = "csirx_top0", "csirx_top1";
+                                       clock-names = "subsys-csirx-top0",
+                                                     "subsys-csirx-top1";
                                        #power-domain-cells = <0>;
                                };
 
@@ -942,7 +943,8 @@
                                        reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
                                        clocks = <&topckgen CLK_TOP_AUDIODSP>,
                                                 <&topckgen CLK_TOP_ADSP_BUS>;
-                                       clock-names = "audioadsp", "adsp_bus";
+                                       clock-names = "audioadsp",
+                                                     "subsys-adsp-bus";
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        #power-domain-cells = <1>;
@@ -975,8 +977,11 @@
                                                 <&mmsys CLK_MM_SMI_COMMON>,
                                                 <&mmsys CLK_MM_SMI_GALS>,
                                                 <&mmsys CLK_MM_SMI_IOMMU>;
-                                       clock-names = "disp", "mdp", "smi_infra", "smi_common",
-                                                    "smi_gals", "smi_iommu";
+                                       clock-names = "disp", "mdp",
+                                                     "subsys-smi-infra",
+                                                     "subsys-smi-common",
+                                                     "subsys-smi-gals",
+                                                     "subsys-smi-iommu";
                                        mediatek,infracfg = <&infracfg_ao>;
                                        #address-cells = <1>;
                                        #size-cells = <0>;
@@ -993,15 +998,17 @@
 
                                        power-domain@MT8186_POWER_DOMAIN_CAM {
                                                reg = <MT8186_POWER_DOMAIN_CAM>;
-                                               clocks = <&topckgen CLK_TOP_CAM>,
-                                                        <&topckgen CLK_TOP_SENINF>,
+                                               clocks = <&topckgen CLK_TOP_SENINF>,
                                                         <&topckgen CLK_TOP_SENINF1>,
                                                         <&topckgen CLK_TOP_SENINF2>,
                                                         <&topckgen CLK_TOP_SENINF3>,
+                                                        <&camsys CLK_CAM2MM_GALS>,
                                                         <&topckgen CLK_TOP_CAMTM>,
-                                                        <&camsys CLK_CAM2MM_GALS>;
-                                               clock-names = "cam-top", "cam0", "cam1", "cam2",
-                                                            "cam3", "cam-tm", "gals";
+                                                        <&topckgen CLK_TOP_CAM>;
+                                               clock-names = "cam0", "cam1", "cam2",
+                                                             "cam3", "gals",
+                                                             "subsys-cam-tm",
+                                                             "subsys-cam-top";
                                                mediatek,infracfg = <&infracfg_ao>;
                                                #address-cells = <1>;
                                                #size-cells = <0>;
@@ -1020,9 +1027,9 @@
 
                                        power-domain@MT8186_POWER_DOMAIN_IMG {
                                                reg = <MT8186_POWER_DOMAIN_IMG>;
-                                               clocks = <&topckgen CLK_TOP_IMG1>,
-                                                        <&imgsys1 CLK_IMG1_GALS_IMG1>;
-                                               clock-names = "img-top", "gals";
+                                               clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
+                                                        <&topckgen CLK_TOP_IMG1>;
+                                               clock-names = "gals", "subsys-img-top";
                                                mediatek,infracfg = <&infracfg_ao>;
                                                #address-cells = <1>;
                                                #size-cells = <0>;
@@ -1041,8 +1048,11 @@
                                                         <&ipesys CLK_IPE_LARB20>,
                                                         <&ipesys CLK_IPE_SMI_SUBCOM>,
                                                         <&ipesys CLK_IPE_GALS_IPE>;
-                                               clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
-                                                             "ipe-smi", "ipe-gals";
+                                               clock-names = "subsys-ipe-top",
+                                                             "subsys-ipe-larb0",
+                                                             "subsys-ipe-larb1",
+                                                             "subsys-ipe-smi",
+                                                             "subsys-ipe-gals";
                                                mediatek,infracfg = <&infracfg_ao>;
                                                #power-domain-cells = <0>;
                                        };
@@ -1061,7 +1071,9 @@
                                                clocks = <&topckgen CLK_TOP_WPE>,
                                                         <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
                                                         <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
-                                               clock-names = "wpe0", "larb-ck", "larb-pclk";
+                                               clock-names = "wpe0",
+                                                             "subsys-larb-ck",
+                                                             "subsys-larb-pclk";
                                                mediatek,infracfg = <&infracfg_ao>;
                                                #power-domain-cells = <0>;
                                        };