Merge tag 'hisi-arm64-dt-for-4.13-v2' of git://github.com/hisilicon/linux-hisi into...

[platform/kernel/linux-starfive.git] / arch / arm64 / boot / dts / hisilicon / hi6220.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 5013e4b..f2e218c 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -332,6 +332,19 @@
                        status = "disabled";
                };
 
+               dma0: dma@f7370000 {
+                       compatible = "hisilicon,k3-dma-1.0";
+                       reg = <0x0 0xf7370000 0x0 0x1000>;
+                       #dma-cells = <1>;
+                       dma-channels = <15>;
+                       dma-requests = <32>;
+                       interrupts = <0 84 4>;
+                       clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
+                       dma-no-cci;
+                       dma-type = "hi6220_dma";
+                       status = "ok";
+               };
+
                dual_timer0: timer@f8008000 {
                        compatible = "arm,sp804", "arm,primecell";
                        reg = <0x0 0xf8008000 0x0 0x1000>;
@@ -805,6 +818,19 @@
                        #thermal-sensor-cells = <1>;
                };
 
+               i2s0: i2s@f7118000{
+                       compatible = "hisilicon,hi6210-i2s";
+                       reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
+                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
+                       clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
+                                <&sys_ctrl HI6220_BBPPLL0_DIV>;
+                       clock-names = "dacodec", "i2s-base";
+                       dmas = <&dma0 15 &dma0 14>;
+                       dma-names = "rx", "tx";
+                       hisilicon,sysctrl-syscon = <&sys_ctrl>;
+                       #sound-dai-cells = <1>;
+               };
+
                thermal-zones {
 
                        cls0: cls0 {