Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[platform/kernel/linux-rpi.git] / arch / arm64 / boot / dts / freescale / imx8mm-phyboard-polis-rdk.dts
index 479948f..92e62fe 100644 (file)
        };
 };
 
+/* TPM */
+&ecspi2 {
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       tpm: tpm@0 {
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+               interrupt-parent = <&gpio2>;
+               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpm>;
+               reg = <0>;
+               spi-max-frequency = <43000000>;
+       };
+};
+
 &gpio1 {
        gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
                "", "", "", "RESET_ETHPHY",
 
 &i2c4 {
        clock-frequency = <400000>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c4>;
+       pinctrl-1 = <&pinctrl_i2c4_gpio>;
+       sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 };
 
 /* PCIe */
                >;
        };
 
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x80
+                       MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x80
+                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x80
+                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x00
+               >;
+       };
+
        pinctrl_fan: fan0grp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8        0x16
                >;
        };
 
+       pinctrl_i2c4_gpio: i2c4gpiogrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20        0x1e2
+                       MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0x1e2
+               >;
+       };
+
        pinctrl_leds: leds1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1       0x16
                >;
        };
 
+       pinctrl_tpm: tpmgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11      0x140
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX      0x00
 
        pinctrl_uart3: uart3grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x40
-                       MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x40
+                       MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
+                       MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
                >;
        };