arm64: dts: Add ARM PMU node for exynos7

[platform/kernel/linux-exynos.git] / arch / arm64 / boot / dts / exynos / exynos7.dtsi

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 1628315..d46ac94 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include <dt-bindings/clock/exynos7-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
        compatible = "samsung,exynos7";
@@ -34,28 +35,28 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               cpu_atlas0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57", "arm,armv8";
                        reg = <0x0>;
                        enable-method = "psci";
                };
 
-               cpu@1 {
+               cpu_atlas1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57", "arm,armv8";
                        reg = <0x1>;
                        enable-method = "psci";
                };
 
-               cpu@2 {
+               cpu_atlas2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57", "arm,armv8";
                        reg = <0x2>;
                        enable-method = "psci";
                };
 
-               cpu@3 {
+               cpu_atlas3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a57", "arm,armv8";
                        reg = <0x3>;
@@ -471,12 +472,26 @@
                        status = "disabled";
                };
 
+               arm-pmu {
+                       compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
+                                            <&cpu_atlas2>, <&cpu_atlas3>;
+               };
+
                timer {
                        compatible = "arm,armv8-timer";
-                       interrupts = <1 13 0xff08>,
-                                    <1 14 0xff08>,
-                                    <1 11 0xff08>,
-                                    <1 10 0xff08>;
+                       interrupts = <GIC_PPI 13
+                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 14
+                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 11
+                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 10
+                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
                };
 
                pmu_system_controller: system-controller@105c0000 {