global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

[platform/kernel/u-boot.git] / arch / arm / mach-zynq / cpu.c

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index e5f5577..3b6518c 100644 (file)
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -4,7 +4,10 @@
  * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
  */
 #include <common.h>
+#include <cpu_func.h>
+#include <init.h>
 #include <zynqpl.h>
+#include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
@@ -14,12 +17,12 @@
 #define ZYNQ_SILICON_VER_MASK  0xF0000000
 #define ZYNQ_SILICON_VER_SHIFT 28
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
 xilinx_desc fpga = {
        .family = xilinx_zynq,
        .iface = devcfg,
        .operations = &zynq_op,
+       .flags = FPGA_LEGACY,
 };
 #endif
 
@@ -51,7 +54,7 @@ int arch_cpu_init(void)
        writel(0x757BDF0D, &devcfg_base->unlock);
        writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
-#if (CONFIG_SYS_SDRAM_BASE == 0)
+#if (CFG_SYS_SDRAM_BASE == 0)
        /* remap DDR to zero, FILTERSTART */
        writel(0, &scu_base->filter_start);
 
@@ -76,7 +79,7 @@ unsigned int zynq_get_silicon_version(void)
                                                >> ZYNQ_SILICON_VER_SHIFT;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
        zynq_slcr_cpu_reset();
        while (1)
@@ -108,8 +111,7 @@ static int __maybe_unused cpu_desc_id(void)
 #if defined(CONFIG_ARCH_EARLY_INIT_R)
 int arch_early_init_r(void)
 {
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
        int cpu_id = cpu_desc_id();
 
        if (cpu_id < 0)