* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
*/
#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
#include <zynqpl.h>
+#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
.operations = &zynq_op,
+ .flags = FPGA_LEGACY,
};
#endif
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
-#if (CONFIG_SYS_SDRAM_BASE == 0)
+#if (CFG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
>> ZYNQ_SILICON_VER_SHIFT;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
zynq_slcr_cpu_reset();
while (1)
;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
int cpu_id = cpu_desc_id();
if (cpu_id < 0)
return 0;
}
#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ u32 version;
+ int cpu_id = cpu_desc_id();
+
+ if (cpu_id < 0)
+ return 0;
+
+ version = zynq_get_silicon_version() << 1;
+ if (version > (PCW_SILICON_VERSION_3 << 1))
+ version += 1;
+
+ printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
+ printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+ return 0;
+}
+#endif