ARM: UniPhier: optimize kicking secondary CPUs code

[platform/kernel/u-boot.git] / arch / arm / mach-uniphier / cache_uniphier.c

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c
index 52f3c7c..4bf01bc 100644 (file)
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015      Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -119,20 +120,10 @@ void v7_outer_cache_disable(void)
        writel(tmp, SSCC);
 }
 
-void wakeup_secondary(void);
-
 void enable_caches(void)
 {
        uint32_t reg;
 
-#ifdef CONFIG_UNIPHIER_SMP
-       /*
-        * The secondary CPU must move to DDR,
-        * before L2 disable.
-        * On SPL, the Page Table is located on the L2.
-        */
-       wakeup_secondary();
-#endif
        /*
         * UniPhier SoCs must use L2 cache for init stack pointer.
         * We disable L2 and L1 in this order.