arm: socfpga: Enable all FPGA config support for Arria 10

[platform/kernel/u-boot.git] / arch / arm / mach-uniphier / arm64 / arm-cci500.c

diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
index 607f96a..bf0fad4 100644 (file)
--- a/arch/arm/mach-uniphier/arm64/arm-cci500.c
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -1,17 +1,18 @@
 /*
  * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
  *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
 
+#include "../init.h"
+
 #define CCI500_BASE                    0x5FD00000
 #define CCI500_SLAVE_OFFSET            0x1000
 
@@ -28,13 +29,13 @@ void cci500_init(unsigned int nr_slaves)
                void __iomem *base;
                u32 tmp;
 
-               base = map_sysmem(slave_base, SZ_4K);
+               base = ioremap(slave_base, SZ_4K);
 
                tmp = readl(base);
                tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
                writel(tmp, base);
 
-               unmap_sysmem(base);
+               iounmap(base);
 
                slave_base += CCI500_SLAVE_OFFSET;
        }