* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
* @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
+ * Return: mux value (0-4, or -1 if not found)
*/
int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
* provided.
*
* @param clk_id Clock ID according to tegra124 device tree binding
- * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
*/
enum periph_id clk_id_to_periph_id(int clk_id)
{
* Check a register that we set up to see if clock_early_init() has already
* been called.
*
- * @return true if clock_early_init() was called, false if not
+ * Return: true if clock_early_init() was called, false if not
*/
bool clock_early_init_done(void)
{