+// SPDX-License-Identifier: GPL-2.0+
/*
* sun8i H3 platform dram controller init
*
* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <linux/kconfig.h>
-/*
- * The delay parameters below allow to allegedly specify delay times of some
- * unknown unit for each individual bit trace in each of the four data bytes
- * the 32-bit wide access consists of. Also three control signals can be
- * adjusted individually.
- */
-#define BITS_PER_BYTE 8
-#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
-/* The eight data lines (DQn) plus DM, DQS and DQSN */
-#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
-struct dram_para {
- u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
- u8 row_bits;
- u8 bank_bits;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
- const u8 ac_delays[31];
-};
-
-static inline int ns_to_t(int nanoseconds)
-{
- const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
-
- return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
-}
-
static void mctl_phy_init(u32 val)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
}
}
-static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
- u8 tccd = 2;
- u8 tfaw = ns_to_t(50);
- u8 trrd = max(ns_to_t(10), 4);
- u8 trcd = ns_to_t(15);
- u8 trc = ns_to_t(53);
- u8 txp = max(ns_to_t(8), 3);
- u8 twtr = max(ns_to_t(8), 4);
- u8 trtp = max(ns_to_t(8), 4);
- u8 twr = max(ns_to_t(15), 3);
- u8 trp = ns_to_t(15);
- u8 tras = ns_to_t(38);
- u16 trefi = ns_to_t(7800) / 32;
- u16 trfc = ns_to_t(350);
-
- u8 tmrw = 0;
- u8 tmrd = 4;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 4;
- u8 trasmax = 24;
-
- u8 tcl = 6; /* CL 12 */
- u8 tcwl = 4; /* CWL 8 */
- u8 t_rdata_en = 4;
- u8 wr_latency = 2;
-
- u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
- u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
- u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
-
- u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
- u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
- u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
-
- /* set mode register */
- writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
- writel(0x40, &mctl_ctl->mr[1]);
- writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
- writel(0x0, &mctl_ctl->mr[3]);
-
- if (socid == SOCID_R40)
- writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
-
- /* set DRAM timing */
- writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
- DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
- &mctl_ctl->dramtmg[0]);
- writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
- &mctl_ctl->dramtmg[1]);
- writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
- DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
- &mctl_ctl->dramtmg[2]);
- writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
- &mctl_ctl->dramtmg[3]);
- writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
- DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
- writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
- DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
- &mctl_ctl->dramtmg[5]);
-
- /* set two rank timing */
- clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
- ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
-
- /* set PHY interface timing, write latency and read latency configure */
- writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
- (wr_latency << 0), &mctl_ctl->pitmg[0]);
-
- /* set PHY timing, PTR0-2 use default */
- writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
- writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
-
- /* set refresh timing */
- writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
-}
-
static u32 bin_to_mgray(int val)
{
static const u8 lookup_table[32] = {
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
+ writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
+#if defined CONFIG_SUNXI_DRAM_DDR3
+ MCTL_CR_DDR3 | MCTL_CR_2T |
+#elif defined CONFIG_SUNXI_DRAM_DDR2
+ MCTL_CR_DDR2 | MCTL_CR_2T |
+#elif defined CONFIG_SUNXI_DRAM_LPDDR3
+ MCTL_CR_LPDDR3 | MCTL_CR_1T |
+#else
+#error Unsupported DRAM type!
+#endif
(para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct dram_para para = {
- .dual_rank = 0,
+ .dual_rank = 1,
.bus_full_width = 1,
.row_bits = 15,
.bank_bits = 3,
uint16_t socid = SOCID_H3;
#elif defined(CONFIG_MACH_SUN8I_R40)
uint16_t socid = SOCID_R40;
+ /* Currently we cannot support R40 with dual rank memory */
+ para.dual_rank = 0;
+#elif defined(CONFIG_MACH_SUN8I_V3S)
+ /* TODO: set delays and mbus priority for V3s */
+ uint16_t socid = SOCID_H3;
#elif defined(CONFIG_MACH_SUN50I)
uint16_t socid = SOCID_A64;
#elif defined(CONFIG_MACH_SUN50I_H5)
projects / platform / kernel / u-boot.git / blobdiff