select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+# TODO: try out A80's 8GiB DRAM space
+config SUNXI_DRAM_MAX_SIZE
+ hex
+ default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
+ default 0x80000000
+
choice
prompt "Sunxi SoC Variant"
optional
bool "sun4i (Allwinner A10)"
select CPU_V7A
select ARM_CORTEX_CPU_IS_UP
- select DM_MMC if MMC
- select DM_SCSI if SCSI
select PHY_SUN4I_USB
select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
+ select MMC_SUNXI_HAS_MODE_SWITCH
select SUPPORT_SPL
config MACH_SUN8I_H3
select SUPPORT_SPL
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
+ select PHY_SUN4I_USB
config MACH_SUN8I_V3S
- bool "sun8i (Allwinner V3s)"
+ bool "sun8i (Allwinner V3/V3s/S3/S3L)"
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
+ select SPI
select DM_I2C
+ select DM_SPI if SPI
+ select DM_SPI_FLASH
select PHY_SUN4I_USB
+ select SUN6I_PRCM
select SUNXI_DE2
select SUNXI_GEN_SUN6I
+ select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
select ARM64
select SUPPORT_SPL
select FIT
+ select PHY_SUN4I_USB
select SPL_LOAD_FIT
select DRAM_SUN50I_H6
This allows both the SPL and the U-Boot proper to be entered in
either mode and switch to AArch64 if needed.
-if SUNXI_DRAM_DW
+if SUNXI_DRAM_DW || DRAM_SUN50I_H6
config SUNXI_DRAM_DDR3
bool
config SUNXI_DRAM_DDR3_1333
bool "DDR3 1333"
select SUNXI_DRAM_DDR3
- depends on !MACH_SUN8I_V3S
---help---
This option is the original only supported memory type, which suits
many H3/H5/A64 boards available now.
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H6_LPDDR3
+ bool "LPDDR3 DRAM chips on the H6 DRAM controller"
+ select SUNXI_DRAM_LPDDR3
+ depends on DRAM_SUN50I_H6
+ ---help---
+ This option is the LPDDR3 timing used by the stock boot0 by
+ Allwinner.
+
+config SUNXI_DRAM_H6_DDR3_1333
+ bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
+ select SUNXI_DRAM_DDR3
+ depends on DRAM_SUN50I_H6
+ ---help---
+ This option is the DDR3 timing used by the boot0 on H6 TV boxes
+ which use a DDR3-1333 timing.
+
config SUNXI_DRAM_DDR2_V3S
bool "DDR2 found in V3s chip"
select SUNXI_DRAM_DDR2
config DRAM_ZQ
int "sunxi dram zq value"
- default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+ default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
+ MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
default 127 if MACH_SUN7I
default 14779 if MACH_SUN8I_V3S
- default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
+ default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
---help---
config DRAM_ODT_EN
bool "sunxi dram odt enable"
default y if MACH_SUN8I_A23
+ default y if MACH_SUNXI_H3_H5
default y if MACH_SUN8I_R40
default y if MACH_SUN50I
default y if MACH_SUN50I_H6
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
option, the device tree selection code specific to Pine64 which
utilizes the DRAM size will be enabled.
+config PINEPHONE_DT_SELECTION
+ bool "Enable PinePhone device tree selection code"
+ depends on MACH_SUN50I
+ help
+ Enable this option to automatically select the device tree for the
+ correct PinePhone hardware revision during boot.
+
endif