Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / mach-stm32mp / spl.c

diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index b7e7e92..66a6346 100644 (file)
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -7,7 +7,10 @@
 #include <cpu_func.h>
 #include <dm.h>
 #include <hang.h>
+#include <init.h>
+#include <log.h>
 #include <spl.h>
+#include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <linux/libfdt.h>
@@ -52,6 +55,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
        return MMCSD_MODE_RAW;
 }
 
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 int spl_mmc_boot_partition(const u32 boot_device)
 {
        switch (boot_device) {
@@ -63,6 +67,7 @@ int spl_mmc_boot_partition(const u32 boot_device)
                return -EINVAL;
        }
 }
+#endif
 
 #ifdef CONFIG_SPL_DISPLAY_PRINT
 void spl_display_print(void)
@@ -135,7 +140,8 @@ void board_init_f(ulong dummy)
         * to avoid speculative access and issue in get_ram_size()
         */
        if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
-               mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+               mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+                                               CONFIG_DDR_CACHEABLE_SIZE,
                                                DCACHE_DEFAULT_OPTION);
 }
 
@@ -144,7 +150,7 @@ void spl_board_prepare_for_boot(void)
        dcache_disable();
 }
 
-void spl_board_prepare_for_boot_linux(void)
+void spl_board_prepare_for_linux(void)
 {
        dcache_disable();
 }