#include <cpu_func.h>
#include <debug_uart.h>
#include <env.h>
+#include <init.h>
+#include <log.h>
#include <misc.h>
+#include <net.h>
#include <asm/io.h>
+#include <asm/arch/bsec.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <linux/bitops.h>
/* RCC register */
#define RCC_TZCR (STM32_RCC_BASE + 0x00)
#define PKG_SHIFT 27
#define PKG_MASK GENMASK(2, 0)
+/*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
+ */
+u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-#ifndef CONFIG_STM32MP1_TRUSTED
+#ifndef CONFIG_TFABOOT
static void security_init(void)
{
/* Disable the backup domain write protection */
writel(BIT(0), RCC_MP_AHB5ENSETR);
writel(0x0, GPIOZ_SECCFGR);
}
-#endif /* CONFIG_STM32MP1_TRUSTED */
+#endif /* CONFIG_TFABOOT */
/*
* Debug init
*/
static void dbgmcu_init(void)
{
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+ /*
+ * Freeze IWDG2 if Cortex-A7 is in debug mode
+ * done in TF-A for TRUSTED boot and
+ * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
+ */
+ if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+ }
+}
- /* Freeze IWDG2 if Cortex-A7 is in debug mode */
- setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+void spl_board_init(void)
+{
+ dbgmcu_init();
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
-#if !defined(CONFIG_STM32MP1_TRUSTED) && \
+#if !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* get bootmode from ROM code boot context: saved in TAMP register */
static void update_bootmode(void)
}
/*
+ * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
+ */
+static void early_enable_caches(void)
+{
+ /* I-cache is already enabled in start.S: cpu_init_cp15 */
+
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+
+ dcache_enable();
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ mmu_set_region_dcache_behaviour(
+ ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
+ ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
+ DCACHE_DEFAULT_OPTION);
+ else
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+ CONFIG_DDR_CACHEABLE_SIZE,
+ DCACHE_DEFAULT_OPTION);
+}
+
+/*
* Early system init
*/
int arch_cpu_init(void)
{
u32 boot_mode;
+ early_enable_caches();
+
/* early armv7 timer init: needed for polling */
timer_init();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
- dbgmcu_init();
-#ifndef CONFIG_STM32MP1_TRUSTED
+#ifndef CONFIG_TFABOOT
security_init();
update_bootmode();
#endif
if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#if defined(CONFIG_DEBUG_UART) && \
- !defined(CONFIG_STM32MP1_TRUSTED) && \
+ !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
else
debug_uart_init();
void enable_caches(void)
{
- /* Enable D-cache. I-cache is already enabled in start.S */
+ /* I-cache is already enabled in start.S: icache_enable() not needed */
+
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * update MMU after relocation and enable the data cache
+ * warning: the TLB location udpated in board_f.c::reserve_mmu
+ */
dcache_enable();
}
static u32 read_idc(void)
{
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+ /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
+ if (bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
- return readl(DBGMCU_IDC);
+ return readl(DBGMCU_IDC);
+ }
+
+ if (CONFIG_IS_ENABLED(STM32MP15x))
+ return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
+ else
+ return 0x0;
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
}
u32 get_cpu_rev(void)
u32 get_cpu_type(void)
{
- u32 id;
-
- id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
-
- return (id << 16) | get_cpu_rpn();
+ return (get_cpu_dev() << 16) | get_cpu_rpn();
}
/* Get Package options from OTP */
env_set("boot_device", "nand");
env_set("boot_instance", "0");
break;
+ case BOOT_FLASH_SPINAND:
+ env_set("boot_device", "spi-nand");
+ env_set("boot_instance", "0");
+ break;
case BOOT_FLASH_NOR:
env_set("boot_device", "nor");
env_set("boot_instance", "0");
return -EINVAL;
}
pr_debug("OTP MAC address = %pM\n", enetaddr);
- ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
- if (!ret)
+ ret = eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (ret)
pr_err("Failed to set mac address %pM from OTP: %d\n",
enetaddr, ret);
#endif