Merge branch 'master' of git://git.denx.de/u-boot-sh

[platform/kernel/u-boot.git] / arch / arm / mach-socfpga / spl_gen5.c

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index d6fe7d3..87b76b4 100644 (file)
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -17,20 +16,14 @@
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/nic301.h>
 #include <asm/sections.h>
+#include <debug_uart.h>
 #include <fdtdec.h>
 #include <watchdog.h>
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct scu_registers *scu_regs =
-       (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct nic301_registers *nic301_regs =
-       (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static const struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -43,16 +36,12 @@ u32 spl_boot_device(void)
                return BOOT_DEVICE_RAM;
        case 0x2:       /* NAND Flash (1.8V) */
        case 0x3:       /* NAND Flash (3.0V) */
-               socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
                return BOOT_DEVICE_NAND;
        case 0x4:       /* SD/MMC External Transceiver (1.8V) */
        case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
-               socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
-               socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
                return BOOT_DEVICE_MMC1;
        case 0x6:       /* QSPI Flash (1.8V) */
        case 0x7:       /* QSPI Flash (3.0V) */
-               socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
                return BOOT_DEVICE_SPI;
        default:
                printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -63,7 +52,7 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 u32 spl_boot_mode(const u32 boot_device)
 {
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;
 #else
        return MMCSD_MODE_RAW;
@@ -71,21 +60,12 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-static void socfpga_nic301_slave_ns(void)
-{
-       writel(0x1, &nic301_regs->lwhps2fpgaregs);
-       writel(0x1, &nic301_regs->hps2fpgaregs);
-       writel(0x1, &nic301_regs->acp);
-       writel(0x1, &nic301_regs->rom);
-       writel(0x1, &nic301_regs->ocram);
-       writel(0x1, &nic301_regs->sdrdata);
-}
-
 void board_init_f(ulong dummy)
 {
        const struct cm_config *cm_default_cfg = cm_get_default_config();
-       unsigned long sdram_size;
        unsigned long reg;
+       int ret;
+       struct udevice *dev;
 
        /*
         * First C code to run. Clear fake OCRAM ECC first as SBE
@@ -101,14 +81,8 @@ void board_init_f(ulong dummy)
 
        memset(__bss_start, 0, __bss_end - __bss_start);
 
-       socfpga_nic301_slave_ns();
-
-       /* Configure ARM MPU SNSAC register. */
-       setbits_le32(&scu_regs->sacr, 0xfff);
-
-       /* Remap SDRAM to 0x0 */
-       writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
-       writel(0x1, &pl310->pl310_addr_filter_start);
+       socfpga_sdram_remap_zero();
+       socfpga_pl310_clear();
 
        debug("Freezing all I/O banks\n");
        /* freeze all IO banks */
@@ -116,13 +90,13 @@ void board_init_f(ulong dummy)
 
        /* Put everything into reset but L4WD0. */
        socfpga_per_reset_all();
-       /* Put FPGA bridges into reset too. */
-       socfpga_bridges_reset(1);
 
-       socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-       socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-       socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
+       if (!socfpga_is_booting_from_fpga()) {
+               /* Put FPGA bridges into reset too. */
+               socfpga_bridges_reset(1);
+       }
 
+       socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
        timer_init();
 
        debug("Reconfigure Clock Manager\n");
@@ -144,40 +118,34 @@ void board_init_f(ulong dummy)
        sysmgr_pinmux_init();
        sysmgr_config_warmrstcfgio(0);
 
-       /* De-assert reset for peripherals and bridges based on handoff */
-       reset_deassert_peripherals_handoff();
-       socfpga_bridges_reset(0);
+       /* Set bridges handoff value */
+       socfpga_bridges_set_handoff_regs(true, true, true);
 
        debug("Unfreezing/Thaw all I/O banks\n");
        /* unfreeze / thaw all IO banks */
        sys_mgr_frzctrl_thaw_req();
 
-       /* enable console uart printing */
-       preloader_console_init();
+#ifdef CONFIG_DEBUG_UART
+       socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+       debug_uart_init();
+#endif
 
-       if (sdram_mmr_init_full(0xffffffff) != 0) {
-               puts("SDRAM init failed.\n");
+       ret = spl_early_init();
+       if (ret) {
+               debug("spl_early_init() failed: %d\n", ret);
                hang();
        }
 
-       debug("SDRAM: Calibrating PHY\n");
-       /* SDRAM calibration */
-       if (sdram_calibration_full() == 0) {
-               puts("SDRAM calibration failed.\n");
-               hang();
-       }
+       ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+       if (ret)
+               debug("Reset init failed: %d\n", ret);
 
-       sdram_size = sdram_calculate_size();
-       debug("SDRAM: %ld MiB\n", sdram_size >> 20);
+       /* enable console uart printing */
+       preloader_console_init();
 
-       /* Sanity check ensure correct SDRAM size specified */
-       if (get_ram_size(0, sdram_size) != sdram_size) {
-               puts("SDRAM size check failed!\n");
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               debug("DRAM init failed: %d\n", ret);
                hang();
        }
-
-       socfpga_bridges_reset(1);
-
-       /* Configure simple malloc base pointer into RAM. */
-       gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }