Merge branch 'master' of git://git.denx.de/u-boot-sh

[platform/kernel/u-boot.git] / arch / arm / mach-socfpga / spl_a10.c

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c8e73d4..b820cb0 100644 (file)
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
  */
 
 #include <common.h>
@@ -23,6 +23,11 @@
 #include <fdtdec.h>
 #include <watchdog.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/fpga_manager.h>
+#include <mmc.h>
+#include <memalign.h>
+
+#define FPGA_BUFSIZ    16 * 1024
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
 
 void spl_board_init(void)
 {
+       ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
        /* enable console uart printing */
        preloader_console_init();
        WATCHDOG_RESET();
 
        arch_early_init_r();
+
+       /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+       if (is_fpgamgr_user_mode()) {
+               int ret = config_pins(gd->fdt_blob, "shared");
+
+               if (ret)
+                       return;
+
+               ret = config_pins(gd->fdt_blob, "fpga");
+               if (ret)
+                       return;
+       } else if (!is_fpgamgr_early_user_mode()) {
+               /* Program IOSSM(early IO release) or full FPGA */
+               fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+       }
+
+       /* If the IOSSM/full FPGA is already loaded, start DDR */
+       if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+               ddr_calibration_sequence();
+
+       if (!is_fpgamgr_user_mode())
+               fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 }
 
 void board_init_f(ulong dummy)
@@ -81,6 +110,7 @@ void board_init_f(ulong dummy)
 
        socfpga_init_security_policies();
        socfpga_sdram_remap_zero();
+       socfpga_pl310_clear();
 
        /* Assert reset to all except L4WD0 and L4TIMER0 */
        socfpga_per_reset_all();