Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / arch / arm / mach-socfpga / include / mach / reset_manager.h

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 8e59578..42beaec 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,38 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  */
 
-#ifndef        _RESET_MANAGER_H_
-#define        _RESET_MANAGER_H_
+#ifndef _RESET_MANAGER_H_
+#define _RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
-void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-       u32     status;
-       u32     ctrl;
-       u32     counts;
-       u32     padding1;
-       u32     mpu_mod_reset;
-       u32     per_mod_reset;
-       u32     per2_mod_reset;
-       u32     brg_mod_reset;
-       u32     misc_mod_reset;
-       u32     tstscratch;
-};
-
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
-#else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
-#endif
 
 /*
  * Define a reset identifier, from which a permodrst bank ID
@@ -54,27 +33,15 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)                    \
        (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
-/*
- * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... permodrst
- * 2 ... per2modrst
- * 3 ... brgmodrst
- * 4 ... miscmodrst
- */
-#define RSTMGR_EMAC0           RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1           RSTMGR_DEFINE(1, 1)
-#define RSTMGR_L4WD0           RSTMGR_DEFINE(1, 6)
-#define RSTMGR_OSC1TIMER0      RSTMGR_DEFINE(1, 8)
-#define RSTMGR_UART0           RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0           RSTMGR_DEFINE(1, 18)
-#define RSTMGR_SPIM1           RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI            RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC           RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA             RSTMGR_DEFINE(0, 28)
-#define RSTMGR_SDR             RSTMGR_DEFINE(1, 29)
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/reset_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/reset_manager_s10.h>
+#endif
+
 #endif /* _RESET_MANAGER_H_ */