ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board

[platform/kernel/u-boot.git] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..afc38d5 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -69,6 +69,10 @@ config TARGET_SOCFPGA_ARIES_MCVEVK
        bool "Aries MCVEVK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+       bool "Devboards DBM-SoC1 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_EBV_SOCRATES
        bool "EBV SoCrates (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -108,6 +112,7 @@ config SYS_BOARD
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
@@ -123,6 +128,7 @@ config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
+       default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
        default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -137,6 +143,7 @@ config SYS_CONFIG_NAME
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+       default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO