arm: socfpga: agilex: Enable Agilex SoC build

[platform/kernel/u-boot.git] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 48f02f0..969698c 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,8 +1,17 @@
 if ARCH_SOCFPGA
 
+config ERR_PTR_OFFSET
+       default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
+
 config NR_DRAM_BANKS
        default 1
 
+config SPL_SIZE_LIMIT
+       default 0x10000 if TARGET_SOCFPGA_GEN5
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+       default 0x200 if TARGET_SOCFPGA_GEN5
+
 config SPL_STACK_R_ADDR
        default 0x00800000 if TARGET_SOCFPGA_GEN5
 
@@ -20,6 +29,15 @@ config SYS_TEXT_BASE
        default 0x01000040 if TARGET_SOCFPGA_ARRIA10
        default 0x01000040 if TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_AGILEX
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SET_SMPEN
+       select ARMV8_SPIN_TABLE
+       select CLK
+       select NCORE_CACHE
+       select SPL_CLK if SPL
+
 config TARGET_SOCFPGA_ARRIA5
        bool
        select TARGET_SOCFPGA_GEN5
@@ -39,7 +57,7 @@ config TARGET_SOCFPGA_ARRIA10
        select SPL_SYSCON if SPL
        select ETH_DESIGNWARE_SOCFPGA
        imply FPGA_SOCFPGA
-       imply USE_TINY_PRINTF
+       imply SPL_USE_TINY_PRINTF
 
 config TARGET_SOCFPGA_CYCLONE5
        bool
@@ -49,9 +67,11 @@ config TARGET_SOCFPGA_GEN5
        bool
        select SPL_ALTERA_SDRAM
        imply FPGA_SOCFPGA
+       imply SPL_SIZE_LIMIT_SUBTRACT_GD
+       imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
        imply SPL_STACK_R
        imply SPL_SYS_MALLOC_SIMPLE
-       imply USE_TINY_PRINTF
+       imply SPL_USE_TINY_PRINTF
 
 config TARGET_SOCFPGA_STRATIX10
        bool
@@ -64,6 +84,10 @@ choice
        prompt "Altera SOCFPGA board select"
        optional
 
+config TARGET_SOCFPGA_AGILEX_SOCDK
+       bool "Intel SOCFPGA SoCDK (Agilex)"
+       select TARGET_SOCFPGA_AGILEX
+
 config TARGET_SOCFPGA_ARIES_MCVEVK
        bool "Aries MCVEVK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -92,8 +116,8 @@ config TARGET_SOCFPGA_IS1
        bool "IS1 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
-       bool "samtec VIN|ING FPGA (Cyclone V)"
+config TARGET_SOCFPGA_SOFTING_VINING_FPGA
+       bool "Softing VIN|ING FPGA (Cyclone V)"
        select BOARD_LATE_INIT
        select TARGET_SOCFPGA_CYCLONE5
 
@@ -124,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+       default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -137,9 +162,10 @@ config SYS_BOARD
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
        default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
-       default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+       default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -147,7 +173,7 @@ config SYS_VENDOR
        default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
-       default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
@@ -157,6 +183,7 @@ config SYS_SOC
        default "socfpga"
 
 config SYS_CONFIG_NAME
+       default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -170,6 +197,6 @@ config SYS_CONFIG_NAME
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
        default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
-       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 endif