clocks: qcom: add clocks for SDM845 debug uart

[platform/kernel/u-boot.git] / arch / arm / mach-snapdragon / clock-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h
index d7026aa..2ac53b5 100644 (file)
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -1,24 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Qualcomm APQ8016, APQ8096
+ * Qualcomm APQ8016, APQ8096, SDM845
  *
  * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _CLOCK_SNAPDRAGON_H
 #define _CLOCK_SNAPDRAGON_H
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 
-struct gpll0_ctrl {
+struct pll_vote_clk {
        uintptr_t status;
        int status_bit;
        uintptr_t ena_vote;
        int vote_bit;
 };
 
+struct vote_clk {
+       uintptr_t cbcr_reg;
+       uintptr_t ena_vote;
+       int vote_bit;
+};
 struct bcr_regs {
        uintptr_t cfg_rcgr;
        uintptr_t cmd_rcgr;
@@ -31,9 +36,10 @@ struct msm_clk_priv {
        phys_addr_t base;
 };
 
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
 void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
 void clk_enable_cbc(phys_addr_t cbcr);
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
                          int div, int m, int n, int source);