rockchip: rk3399: spl: ensure that debug_uart_init is called

[platform/kernel/u-boot.git] / arch / arm / mach-rockchip / rk3399-board-spl.c

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 5453b2a..ccc136f 100644 (file)
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -9,6 +9,7 @@
 #include <dm.h>
 #include <ram.h>
 #include <spl.h>
+#include <spl_gpio.h>
 #include <syscon.h>
 #include <asm/io.h>
 #include <asm/arch/bootrom.h>
@@ -16,6 +17,7 @@
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/periph.h>
+#include <asm/arch/sys_proto.h>
 #include <dm/pinctrl.h>
 
 void board_return_to_bootrom(void)
@@ -128,7 +130,13 @@ void secure_timer_init(void)
 void board_debug_uart_init(void)
 {
 #define GRF_BASE       0xff770000
+#define GPIO0_BASE     0xff720000
+#define PMUGRF_BASE    0xff320000
        struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+       struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+       struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+#endif
 
 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
        /* Enable early UART0 on the RK3399 */
@@ -139,6 +147,20 @@ void board_debug_uart_init(void)
                     GRF_GPIO2C1_SEL_MASK,
                     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
 #else
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+       rk_setreg(&grf->io_vsel, 1 << 0);
+
+       /*
+        * Let's enable these power rails here, we are already running the SPI
+        * Flash based code.
+        */
+       spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
+       spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
+
+       spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
+       spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
        /* Enable early UART2 channel C on the RK3399 */
        rk_clrsetreg(&grf->gpio4c_iomux,
                     GRF_GPIO4C3_SEL_MASK,
@@ -163,6 +185,22 @@ void board_init_f(ulong dummy)
 
 #define EARLY_UART
 #ifdef EARLY_UART
+       debug_uart_init();
+
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+       int sum, i;
+
+       /*
+        * Add a delay and ensure that the compiler does not optimise this out.
+        * This is needed since the power rails tail a while to turn on, and
+        * we get garbage serial output otherwise.
+        */
+       sum = 0;
+       for (i = 0; i < 150000; i++)
+               sum += i;
+       gru_dummy_function(sum);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
        /*
         * Debug UART can be used from here if required:
         *
@@ -171,7 +209,6 @@ void board_init_f(ulong dummy)
         * printhex8(0x1234);
         * printascii("string");
         */
-       debug_uart_init();
        printascii("U-Boot SPL board init\n");
 #endif