CONFIG_SPL_SYS_[DI]CACHE_OFF: add

[platform/kernel/u-boot.git] / arch / arm / mach-omap2 / omap5 / sec_entry_cpu1.S

diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
index 6dc92a6..32de9d3 100644 (file)
--- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -16,7 +16,7 @@
 
 .arch_extension sec
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 .global flush_dcache_range
 #endif
 
@@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1)
        push    {r4, r5, lr}
        ldr     r4, =omap_smc_sec_cpu1_args
        stm     r4, {r0,r1,r2,r3}       @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        mov     r0, r4
        mov     r1, #CONFIG_SYS_CACHELINE_SIZE
        add     r1, r0, r1              @ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1)
  */
 .section .data
 omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        .balign CONFIG_SYS_CACHELINE_SIZE
        .rept  CONFIG_SYS_CACHELINE_SIZE/4
        .word 0