Prepare v2023.10

[platform/kernel/u-boot.git] / arch / arm / mach-omap2 / am33xx / ddr.c

diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index c70b6fe..5f970d9 100644 (file)
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -5,11 +5,14 @@
  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  */
 
+#include <common.h>
+#include <log.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/emif.h>
+#include <linux/delay.h>
 
 /**
  * Base address for EMIF instances
@@ -179,14 +182,6 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  */
 void config_sdram(const struct emif_regs *regs, int nr)
 {
-#ifdef CONFIG_TI816X
-       writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-       writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
-       writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
-       writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
-       writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
-       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
-#else
        if (regs->zq_config) {
                writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
                writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
@@ -208,7 +203,6 @@ void config_sdram(const struct emif_regs *regs, int nr)
        /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
        if (regs->ocp_config)
                writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
-#endif
 }
 
 /**
@@ -311,8 +305,8 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
-       writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
-       writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+       writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+       writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 
        /*
         * Sequence to ensure that the PHY is again in a known state after