Merge branch 'master' of git://git.denx.de/u-boot

[platform/kernel/u-boot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index ea83e21..895ad92 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
 };
 
+void lowlevel_init(void)
+{
+       /*
+        * Dummy implementation, we only need LOWLEVEL_INIT
+        * on Armada to configure CP15 in start.S / cpu_init_cp15()
+        */
+}
+
 void reset_cpu(unsigned long ignored)
 {
        struct mvebu_system_registers *reg =
@@ -214,32 +222,39 @@ static void setup_usb_phys(void)
 
 int arch_cpu_init(void)
 {
-#ifndef CONFIG_SPL_BUILD
-       if (mvebu_soc_family() == MVEBU_SOC_A38X) {
-               struct pl310_regs *const pl310 =
-                       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#if !defined(CONFIG_SPL_BUILD)
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-               /*
-                * Only with disabled MMU its possible to switch the base
-                * register address on Armada 38x. Without this the SDRAM
-                * located at >= 0x4000.0000 is also not accessible, as its
-                * still locked to cache.
-                *
-                * So to fully release / unlock this area from cache, we need
-                * to first flush all caches, then disable the MMU and
-                * disable the L2 cache.
-                */
-               icache_disable();
-               dcache_disable();
-               mmu_disable();
-               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-       }
+       /*
+        * Only with disabled MMU its possible to switch the base
+        * register address on Armada 38x. Without this the SDRAM
+        * located at >= 0x4000.0000 is also not accessible, as its
+        * still locked to cache.
+        */
+       mmu_disable();
 #endif
 
        /* Linux expects the internal registers to be at 0xf1000000 */
        writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
        set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
+#if !defined(CONFIG_SPL_BUILD)
+       /*
+        * From this stage on, the SoC detection is working. As we have
+        * configured the internal register base to the value used
+        * in the macros / defines in the U-Boot header (soc.h).
+        */
+
+       /*
+        * To fully release / unlock this area from cache, we need
+        * to flush all caches and disable the L2 cache.
+        */
+       icache_disable();
+       dcache_disable();
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+#endif
+
        /*
         * We need to call mvebu_mbus_probe() before calling
         * update_sdram_window_sizes() as it disables all previously