global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / arm / mach-imx / mx7 / clock.c

diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 8150faa..88f6fe0 100644 (file)
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -1,14 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  *
  * Author:
  *     Peng Fan <Peng.Fan@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
 #include <div64.h>
+#include <log.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -20,16 +23,16 @@ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
                                         ANATOP_BASE_ADDR;
 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
        gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
        gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #else
        gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
@@ -54,7 +57,7 @@ static u32 get_ipg_clk(void)
 
 u32 imx_get_uartclk(void)
 {
-       return get_root_clk(UART1_CLK_ROOT);
+       return get_root_clk(UART_CLK_ROOT);
 }
 
 u32 imx_get_fecclk(void)
@@ -914,7 +917,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
                }
 
                if (5 == i) {
-                       printf("Fail to set rate to %dkhz", freq);
+                       printf("Fail to set rate to %u kHz", freq);
                        return;
                }
        }
@@ -934,7 +937,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
        }
 
        if (best == 0) {
-               printf("Fail to set rate to %dkhz", freq);
+               printf("Fail to set rate to %u kHz", freq);
                return;
        }
 
@@ -1075,7 +1078,7 @@ void clock_init(void)
        }
 }
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 void hab_caam_clock_enable(unsigned char enable)
 {
        if (enable)
@@ -1096,10 +1099,12 @@ void epdc_clock_disable(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
-int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+                     char *const argv[])
 {
        u32 freq;
        freq = decode_pll(PLL_CORE, MXC_HCLK);
@@ -1111,17 +1116,17 @@ int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        printf("\n");
 
-       printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
-       printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+       printf("IPG        %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+       printf("UART       %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 #ifdef CONFIG_MXC_SPI
-       printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+       printf("CSPI       %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
 #endif
-       printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
-       printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
-       printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-       printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
-       printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
-       printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+       printf("AHB        %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+       printf("AXI        %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+       printf("DDR        %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+       printf("USDHC1     %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+       printf("USDHC2     %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+       printf("USDHC3     %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
 
        return 0;
 }
@@ -1131,3 +1136,4 @@ U_BOOT_CMD(
        "display clocks",
        ""
 );
+#endif