Prepare v2023.10

[platform/kernel/u-boot.git] / arch / arm / mach-imx / imx_bootaux.c

diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 433c1f8..f7b14ca 100644 (file)
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -14,6 +14,7 @@
 #include <linux/compiler.h>
 #include <cpu_func.h>
 
+#ifndef CONFIG_IMX8
 /* Just to avoid build error */
 #if IS_ENABLED(CONFIG_IMX8M)
 #define SRC_M4C_NON_SCLR_RST_MASK      BIT(0)
@@ -21,11 +22,14 @@
 #define SRC_M4_REG_OFFSET              0
 #endif
 
-const __weak struct rproc_att hostmap[] = { };
+__weak const struct rproc_att *imx_bootaux_get_hostmap(void)
+{
+       return NULL;
+}
 
 static const struct rproc_att *get_host_mapping(unsigned long auxcore)
 {
-       const struct rproc_att *mmap = hostmap;
+       const struct rproc_att *mmap = imx_bootaux_get_hostmap();
 
        while (mmap && mmap->size) {
                if (mmap->da <= auxcore &&
@@ -42,7 +46,7 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore)
  * is valid, returns the entry point address.
  * Translates load addresses in the elf file to the U-Boot address space.
  */
-static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack)
+static u32 load_elf_image_m_core_phdr(unsigned long addr, u32 *stack)
 {
        Elf32_Ehdr *ehdr; /* ELF header structure pointer */
        Elf32_Phdr *phdr; /* Program header structure pointer */
@@ -92,7 +96,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack
 
 int arch_auxiliary_core_up(u32 core_id, ulong addr)
 {
-       ulong stack, pc;
+       u32 stack, pc;
 
        if (!addr)
                return -EINVAL;
@@ -118,18 +122,18 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
                pc = *(u32 *)(addr + 4);
        }
 
-       printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
+       printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
               stack, pc);
 
-       /* Set the stack and pc to M4 bootROM */
-       writel(stack, M4_BOOTROM_BASE_ADDR);
-       writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+       /* Set the stack and pc to MCU bootROM */
+       writel(stack, MCU_BOOTROM_BASE_ADDR);
+       writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
 
        flush_dcache_all();
 
-       /* Enable M4 */
+       /* Enable MCU */
        if (IS_ENABLED(CONFIG_IMX8M)) {
-               arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
+               arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL);
        } else {
                clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
                                SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
@@ -144,7 +148,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
        unsigned int val;
 
        if (IS_ENABLED(CONFIG_IMX8M)) {
-               arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
+               arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res);
                return res.a0;
        }
 
@@ -155,30 +159,34 @@ int arch_auxiliary_core_check_up(u32 core_id)
 
        return 1;
 }
-
+#endif
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC
  * as the first two words.
  *
- * Per the cortex-M reference manual, the reset vector of M4 needs
- * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
- * of that vector.  So to boot M4, the A core must build the M4's reset
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector.  So to boot M4/M7, the A core must build the M4/M7's reset
  * vector with getting the PC and SP from image and filling them to
- * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
- * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
- * accessing the M4 TCMUL.
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
  */
 static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
                      char *const argv[])
 {
        ulong addr;
        int ret, up;
+       u32 core = 0;
 
        if (argc < 2)
                return CMD_RET_USAGE;
 
-       up = arch_auxiliary_core_check_up(0);
+       if (argc > 2)
+               core = simple_strtoul(argv[2], NULL, 10);
+
+       up = arch_auxiliary_core_check_up(core);
        if (up) {
                printf("## Auxiliary core is already up\n");
                return CMD_RET_SUCCESS;
@@ -189,7 +197,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
        if (!addr)
                return CMD_RET_FAILURE;
 
-       ret = arch_auxiliary_core_up(0, addr);
+       ret = arch_auxiliary_core_up(core, addr);
        if (ret)
                return CMD_RET_FAILURE;
 
@@ -199,5 +207,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 U_BOOT_CMD(
        bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
        "Start auxiliary core",
-       ""
+       "<address> [<core>]\n"
+       "   - start auxiliary core [<core>] (default 0),\n"
+       "     at address <address>\n"
 );