Merge branch 'next/soc' into HEAD

[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / arm / mach-exynos / clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 404c53d..618d0aa 100644 (file)
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
 
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -672,10 +667,6 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
-               .name           = "gps",
-               .enable         = exynos5_clk_ip_gps_ctrl,
-               .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
-       }, {
                .name           = "nfcon",
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 22),