rpi5: Use devicetree as alternative way to read IO base addresses

[platform/kernel/u-boot.git] / arch / arm / mach-bcm283x / init.c

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index cf4c5b2..0fb06b7 100644 (file)
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -11,9 +11,10 @@
 #include <init.h>
 #include <dm/device.h>
 #include <fdt_support.h>
+#include <asm/global_data.h>
 
 #define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS       0x600000000UL
-#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE       0x800000UL
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE       0x400000UL
 
 #ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
@@ -67,6 +68,36 @@ static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
        }
 };
 
+static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = {
+       {
+               /* First 1GB of DRAM */
+               .virt = 0x00000000UL,
+               .phys = 0x00000000UL,
+               .size = 0x40000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               /* Beginning of AXI bus where uSD controller lives */
+               .virt = 0x1000000000UL,
+               .phys = 0x1000000000UL,
+               .size = 0x0002000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* SoC bus */
+               .virt = 0x107c000000UL,
+               .phys = 0x107c000000UL,
+               .size = 0x0004000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
 struct mm_region *mem_map = bcm283x_mem_map;
 
 /*
@@ -77,6 +108,7 @@ static const struct udevice_id board_ids[] = {
        { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
        { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
        { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
+       { .compatible = "brcm,bcm2712", .data = (ulong)&bcm2712_mem_map},
        { },
 };
 
@@ -114,7 +146,11 @@ static void rpi_update_mem_map(void)
 static void rpi_update_mem_map(void) {}
 #endif
 
-unsigned long rpi_bcm283x_base = 0x3f000000;
+/* Default bcm283x devices addresses */
+unsigned long rpi_mbox_base  = 0x3f00b880;
+unsigned long rpi_sdhci_base = 0x3f300000;
+unsigned long rpi_wdog_base  = 0x3f100000;
+unsigned long rpi_timer_base = 0x3f003000;
 
 int arch_cpu_init(void)
 {
@@ -125,27 +161,73 @@ int arch_cpu_init(void)
 
 int mach_cpu_init(void)
 {
-       int ret, soc_offset;
+       int ret, soc, offset;
        u64 io_base, size;
 
        rpi_update_mem_map();
 
        /* Get IO base from device tree */
-       soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
-       if (soc_offset < 0)
-               return soc_offset;
+       soc = fdt_path_offset(gd->fdt_blob, "/soc");
+       if (soc < 0)
+               return soc;
 
-       ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
-                               &io_base, &size);
+       ret = fdt_read_range((void *)gd->fdt_blob, soc, 0, NULL,
+                            &io_base, &size);
        if (ret)
                return ret;
 
-       rpi_bcm283x_base = io_base;
+       rpi_mbox_base  = io_base + 0x00b880;
+       rpi_sdhci_base = io_base + 0x300000;
+       rpi_wdog_base  = io_base + 0x100000;
+       rpi_timer_base = io_base + 0x003000;
+
+       offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
+                                              "brcm,bcm2835-mbox");
+       if (offset > soc)
+               rpi_mbox_base = fdt_get_base_address(gd->fdt_blob, offset);
+
+       offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
+                                              "brcm,bcm2835-sdhci");
+       if (offset > soc)
+               rpi_sdhci_base = fdt_get_base_address(gd->fdt_blob, offset);
+
+       offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
+                                              "brcm,bcm2835-system-timer");
+       if (offset > soc)
+               rpi_timer_base = fdt_get_base_address(gd->fdt_blob, offset);
+
+       offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
+                                              "brcm,bcm2712-pm");
+       if (offset > soc)
+               rpi_wdog_base = fdt_get_base_address(gd->fdt_blob, offset);
 
        return 0;
 }
 
 #ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT       0xffc00000UL
+#include <addr_map.h>
+#include <asm/system.h>
+
+int init_addr_map(void)
+{
+       mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+                                            BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+                                            BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+                                            DCACHE_OFF);
+
+       /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+       addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
+       /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+       addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+                         BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+                         BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+
+       return 0;
+}
+#endif
+
 void enable_caches(void)
 {
        dcache_enable();