+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - common relocation function for AArch64 U-Boot
*
* (C) Copyright 2013
* Albert ARIBAUD <albert.u.boot@aribaud.net>
* David Feng <fenghua@phytium.com.cn>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
/*
* Copy u-boot from flash to RAM
*/
- ldr x1, =__image_copy_start /* x1 <- SRC &__image_copy_start */
- subs x9, x0, x1 /* x9 <- relocation offset */
- b.eq relocate_done /* skip relocation */
- ldr x2, =__image_copy_end /* x2 <- SRC &__image_copy_end */
+ adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
+ add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
+ subs x9, x0, x1 /* x9 <- Run to copy offset */
+ b.eq relocate_done /* skip relocation */
+ /*
+ * Don't ldr x1, __image_copy_start here, since if the code is already
+ * running at an address other than it was linked to, that instruction
+ * will load the relocated value of __image_copy_start. To
+ * correctly apply relocations, we need to know the linked value.
+ *
+ * Linked &__image_copy_start, which we know was at
+ * CONFIG_SYS_TEXT_BASE, which is stored in _TEXT_BASE, as a non-
+ * relocated value, since it isn't a symbol reference.
+ */
+ ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */
+ subs x9, x0, x1 /* x9 <- Link to copy offset */
+ adrp x1, __image_copy_start /* x1 <- address bits [31:12] */
+ add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */
+ adrp x2, __image_copy_end /* x2 <- address bits [31:12] */
+ add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */
copy_loop:
ldp x10, x11, [x1], #16 /* copy from source address [x1] */
stp x10, x11, [x0], #16 /* copy to target address [x0] */
/*
* Fix .rela.dyn relocations
*/
- ldr x2, =__rel_dyn_start /* x2 <- SRC &__rel_dyn_start */
- ldr x3, =__rel_dyn_end /* x3 <- SRC &__rel_dyn_end */
+ adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */
+ add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */
+ adrp x3, __rel_dyn_end /* x3 <- address bits [31:12] */
+ add x3, x3, :lo12:__rel_dyn_end /* x3 <- address bits [11:00] */
fixloop:
ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */
isb sy
4: ldp x0, x1, [sp, #16]
bl __asm_flush_dcache_range
-5: ldp x29, x30, [sp],#16
+ bl __asm_flush_l3_dcache
+5: ldp x29, x30, [sp],#32
ret
ENDPROC(relocate_code)