Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / arch / arm / include / asm / omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index f33f28b..5e2f027 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -4,23 +4,7 @@
  *
  * Aneesh V <aneesh@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef        _OMAP_COMMON_H_
 #define        _OMAP_COMMON_H_
@@ -29,7 +13,7 @@
 
 #include <common.h>
 
-#define NUM_SYS_CLKS   8
+#define NUM_SYS_CLKS   7
 
 struct prcm_regs {
        /* cm1.ckgen */
@@ -89,6 +73,7 @@ struct prcm_regs {
        u32 cm_ssc_deltamstep_dpll_ddrphy;
        u32 cm_clkmode_dpll_dsp;
        u32 cm_shadow_freq_config1;
+       u32 cm_clkmode_dpll_gmac;
        u32 cm_mpu_mpu_clkctrl;
 
        /* cm1.dsp */
@@ -303,6 +288,7 @@ struct prcm_regs {
        /* l4 wkup regs */
        u32 cm_abe_pll_ref_clksel;
        u32 cm_sys_clksel;
+       u32 cm_abe_pll_sys_clksel;
        u32 cm_wkup_clkstctrl;
        u32 cm_wkup_l4wkup_clkctrl;
        u32 cm_wkup_wdtimer1_clkctrl;
@@ -350,10 +336,22 @@ struct prcm_regs {
        u32 cm_l3init_usbphy_clkctrl;
        u32 cm_l4per_mcbsp4_clkctrl;
        u32 prm_vc_cfg_channel;
+
+       /* SCRM stuff, used by some boards */
+       u32 scrm_auxclk0;
+       u32 scrm_auxclk1;
+
+       /* GMAC Clk Ctrl */
+       u32 cm_gmac_gmac_clkctrl;
+       u32 cm_gmac_clkstctrl;
 };
 
 struct omap_sys_ctrl_regs {
        u32 control_status;
+       u32 control_core_mac_id_0_lo;
+       u32 control_core_mac_id_0_hi;
+       u32 control_core_mac_id_1_lo;
+       u32 control_core_mac_id_1_hi;
        u32 control_std_fuse_opp_vdd_mpu_2;
        u32 control_core_mmr_lock1;
        u32 control_core_mmr_lock2;
@@ -400,6 +398,7 @@ struct omap_sys_ctrl_regs {
        u32 control_ddrio_0;
        u32 control_ddrio_1;
        u32 control_ddrio_2;
+       u32 control_ddr_control_ext_0;
        u32 control_lpddr2io1_0;
        u32 control_lpddr2io1_1;
        u32 control_lpddr2io1_2;
@@ -493,6 +492,7 @@ struct dplls {
        const struct dpll_params *iva;
        const struct dpll_params *usb;
        const struct dpll_params *ddr;
+       const struct dpll_params *gmac;
 };
 
 struct pmic_data {
@@ -622,6 +622,7 @@ static inline u8 is_omap54xx(void)
 #define OMAP4430_ES2_3 0x44300230
 #define OMAP4460_ES1_0 0x44600100
 #define OMAP4460_ES1_1 0x44600110
+#define OMAP4470_ES1_0 0x44700100
 
 /* omap5 */
 #define OMAP5430_SILICON_ID_INVALID    0
@@ -636,7 +637,6 @@ static inline u8 is_omap54xx(void)
 /*
  * SRAM scratch space entries
  */
-#define SRAM_SCRATCH_SPACE_ADDR                NON_SECURE_SRAM_START
 #define OMAP_SRAM_SCRATCH_OMAP_REV     SRAM_SCRATCH_SPACE_ADDR
 #define OMAP_SRAM_SCRATCH_EMIF_SIZE    (SRAM_SCRATCH_SPACE_ADDR + 0x4)
 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM   (SRAM_SCRATCH_SPACE_ADDR + 0xC)