u32 cm_l3init_hsusbotg_clkctrl;
u32 cm_l3init_hsusbtll_clkctrl;
u32 cm_l3init_p1500_clkctrl;
+ u32 cm_l3init_sata_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
u32 control_usbotghs_ctrl;
+ u32 control_phy_power_sata;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
+extern struct dplls dra7xx_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+extern struct pmic_data tps659038;
+
void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
-/* HW Init Context */
-#define OMAP_INIT_CONTEXT_SPL 0
-#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
-#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
-#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
+void usb_fake_mac_from_die_id(u32 *id);
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
return *omap_si_rev;
}
+#define OMAP44xx 0x44000000
+
+static inline u8 is_omap44xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFF000000) == OMAP44xx;
+};
+
#define OMAP54xx 0x54000000
static inline u8 is_omap54xx(void)
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
}
+
+#define DRA7XX 0x07000000
+
+static inline u8 is_dra7xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
#endif
/*
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
+#define DRA752_ES1_1 0x07520110
+#define DRA722_ES1_0 0x07220100
/*
* SRAM scratch space entries