arm: omap2plus: Move CONFIG_SYS_PTV out of CONFIG namespace

[platform/kernel/u-boot.git] / arch / arm / include / asm / omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8b296c9..17fdfbc 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -1,19 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2010
  * Texas Instruments, <www.ti.com>
  *
  * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef        _OMAP_COMMON_H_
 #define        _OMAP_COMMON_H_
 
 #ifndef __ASSEMBLY__
 
-#include <common.h>
+#include <linux/types.h>
 
 #define NUM_SYS_CLKS   7
+#define SYS_PTV                2       /* Divisor: 2^(PTV+1) => 8 */
+
+struct bd_info;
 
 struct prcm_regs {
        /* cm1.ckgen */
@@ -361,6 +363,10 @@ struct prcm_regs {
        /* IPU */
        u32 cm_ipu_clkstctrl;
        u32 cm_ipu_i2c5_clkctrl;
+       u32 cm_ipu1_clkstctrl;
+       u32 cm_ipu1_ipu1_clkctrl;
+       u32 cm_ipu2_clkstctrl;
+       u32 cm_ipu2_ipu2_clkctrl;
 
        /*l3main1 edma*/
        u32 cm_l3main1_tptc1_clkctrl;
@@ -597,6 +603,7 @@ extern struct prcm_regs const dra7xx_prcm;
 extern struct dplls const **dplls_data;
 extern struct dplls dra7xx_dplls;
 extern struct dplls dra72x_dplls;
+extern struct dplls dra76x_dplls;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
 extern struct omap_sys_ctrl_regs const **ctrl;
@@ -630,6 +637,12 @@ void do_disable_clocks(u32 const *clk_domains,
                       u8 wait_for_disable);
 #endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
 
+void do_enable_ipu_clocks(u32 const *clk_domains,
+                         u32 const *clk_modules_hw_auto,
+                         u32 const *clk_modules_explicit_en,
+                         u8 wait_for_enable);
+void enable_ipu1_clocks(void);
+void enable_ipu2_clocks(void);
 void setup_post_dividers(u32 const base,
                        const struct dpll_params *params);
 u32 omap_ddr_clk(void);
@@ -683,9 +696,9 @@ void omap_die_id(unsigned int *die_id);
 void gpi2c_init(void);
 
 /* Common FDT Fixups */
-int ft_hs_disable_rng(void *fdt, bd_t *bd);
-int ft_hs_fixup_dram(void *fdt, bd_t *bd);
-int ft_hs_add_tee(void *fdt, bd_t *bd);
+int ft_hs_disable_rng(void *fdt, struct bd_info *bd);
+int ft_hs_fixup_dram(void *fdt, struct bd_info *bd);
+int ft_hs_add_tee(void *fdt, struct bd_info *bd);
 
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP           0
@@ -743,6 +756,18 @@ static inline u8 is_dra76x(void)
        extern u32 *const omap_si_rev;
        return (*omap_si_rev & 0xFFF00000) == DRA76X;
 }
+
+static inline u8 is_dra76x_abz(void)
+{
+       extern u32 *const omap_si_rev;
+       return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+       extern u32 *const omap_si_rev;
+       return (*omap_si_rev & 0xF) == 3;
+}
 #endif
 
 /*
@@ -776,7 +801,10 @@ static inline u8 is_dra76x(void)
 #define DRA752_ES2_0   0x07520200
 #define DRA722_ES1_0   0x07220100
 #define DRA722_ES2_0   0x07220200
+#define DRA722_ES2_1   0x07220210
 
+#define DRA762_ABZ_ES1_0       0x07620102
+#define DRA762_ACD_ES1_0       0x07620103
 /*
  * silicon device type
  * Moving to common from cpu.h, since it is shared by various omap devices