#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
- is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \
- is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5))
+ is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
-#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7))
#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
-#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#ifdef CONFIG_MX6
-#define IMX6_SRC_GPR10_BMODE BIT(28)
+#define IMX6_SRC_GPR10_BMODE BIT(28)
+#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define IMX6_BMODE_MASK GENMASK(7, 0)
#define IMX6_BMODE_SHIFT 4
#endif /* CONFIG_MX6 */
+#ifdef CONFIG_MX7
+#define IMX7_SRC_GPR10_BMODE BIT(28)
+#define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
+#endif
+
/* address translation table */
struct rproc_att {
u32 da; /* device address (From Cortex M4 view) */
void init_snvs(void);
void imx_wdog_disable_powerdown(void);
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size);
+
int arch_auxiliary_core_check_up(u32 core_id);
int board_mmc_get_env_dev(int devno);