#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
#define EMIF_REG_FAST_INIT_SHIFT 29
#define EMIF_REG_FAST_INIT_MASK (1 << 29)
+#define EMIF_REG_LEVLING_TO_SHIFT 4
+#define EMIF_REG_LEVELING_TO_MASK (7 << 4)
#define EMIF_REG_PHY_DLL_READY_SHIFT 2
#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
+/* EMIF_PHY_CTRL_36 */
+#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8)
+
+#define PHY_RDDQS_RATIO_REGS 5
+#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5
+#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10
+
/*Leveling Fields */
#define DDR3_WR_LVL_INT 0x73
#define DDR3_RD_LVL_INT 0x33
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
u32 padding9[6];
- u32 emif_ddr_phy_status[21];
- u32 padding10[27];
+ u32 emif_ddr_phy_status[28];
+ u32 padding10[20];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
- u32 padding[22];
- u32 emif_ddr_fifo_misaligned_clear_1;
- u32 emif_ddr_fifo_misaligned_clear_2;
+ u32 emif_ddr_ext_phy_ctrl_25;
+ u32 emif_ddr_ext_phy_ctrl_25_shdw;
+ u32 emif_ddr_ext_phy_ctrl_26;
+ u32 emif_ddr_ext_phy_ctrl_26_shdw;
+ u32 emif_ddr_ext_phy_ctrl_27;
+ u32 emif_ddr_ext_phy_ctrl_27_shdw;
+ u32 emif_ddr_ext_phy_ctrl_28;
+ u32 emif_ddr_ext_phy_ctrl_28_shdw;
+ u32 emif_ddr_ext_phy_ctrl_29;
+ u32 emif_ddr_ext_phy_ctrl_29_shdw;
+ u32 emif_ddr_ext_phy_ctrl_30;
+ u32 emif_ddr_ext_phy_ctrl_30_shdw;
+ u32 emif_ddr_ext_phy_ctrl_31;
+ u32 emif_ddr_ext_phy_ctrl_31_shdw;
+ u32 emif_ddr_ext_phy_ctrl_32;
+ u32 emif_ddr_ext_phy_ctrl_32_shdw;
+ u32 emif_ddr_ext_phy_ctrl_33;
+ u32 emif_ddr_ext_phy_ctrl_33_shdw;
+ u32 emif_ddr_ext_phy_ctrl_34;
+ u32 emif_ddr_ext_phy_ctrl_34_shdw;
+ u32 emif_ddr_ext_phy_ctrl_35;
+ u32 emif_ddr_ext_phy_ctrl_35_shdw;
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36;
+ u32 emif_ddr_fifo_misaligned_clear_1;
+ };
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36_shdw;
+ u32 emif_ddr_fifo_misaligned_clear_2;
+ };
};
struct dmm_lisa_map_regs {
((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
- ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
& EMIF_REG_LP_MODE_MASK) |\
((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
& EMIF_REG_SR_TIM_SHDW_MASK) |\
((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
- & EMIF_REG_PD_TIM_SHDW_MASK) |\
- ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
& EMIF_REG_PD_TIM_SHDW_MASK))
/* EMIF_L3_CONFIG register value */
u32 sdram_config;
u32 sdram_config2;
u32 ref_ctrl;
+ u32 ref_ctrl_final;
u32 sdram_tim1;
u32 sdram_tim2;
u32 sdram_tim3;
* which is typically the case. So it is sufficient to get
* SDRAM type from EMIF1.
*/
-static inline u32 emif_sdram_type(void)
+static inline u32 emif_sdram_type(u32 sdram_config)
{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- return (readl(&emif->emif_sdram_config) &
- EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+ return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK)
+ >> EMIF_REG_SDRAM_TYPE_SHIFT;
}
/* assert macros */
#endif
void config_data_eye_leveling_samples(u32 emif_base);
-u32 emif_sdram_type(void);
const struct read_write_regs *get_bug_regs(u32 *iterations);
#endif