#include <asm/system.h>
+#ifndef CONFIG_ARM64
+
/*
* Invalidate L2 Cache using co-proc instruction
*/
void set_section_dcache(int section, enum dcache_option option);
void dram_bank_mmu_setup(int bank);
+
+#endif
+
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified