#define CCM_REG_CTRL_MASK 0xffffffff
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT 1
+#define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT 1