Convert CONFIG_PHYLIB et al to Kconfig

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-tegra / pinmux.h

diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index d87da10..4b6e841 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -1,13 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2010-2014
  * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #ifndef _TEGRA_PINMUX_H_
 #define _TEGRA_PINMUX_H_
 
+#include <linux/types.h>
+
 #include <asm/arch/tegra.h>
 
 /* The pullup/pulldown state of a pin group */
@@ -63,6 +64,14 @@ enum pmux_pin_rcv_sel {
 };
 #endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+enum pmux_pin_e_io_hv {
+       PMUX_PIN_E_IO_HV_DEFAULT = 0,
+       PMUX_PIN_E_IO_HV_NORMAL,
+       PMUX_PIN_E_IO_HV_HIGH,
+};
+#endif
+
 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 /* Defines a pin group cfg's low-power mode select */
 enum pmux_lpmd {
@@ -119,6 +128,9 @@ struct pmux_pingrp_config {
        u32 rcv_sel:2;          /* select between High and Normal  */
                                /* VIL/VIH receivers */
 #endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+       u32 e_io_hv:2;          /* select 3.3v tolerant receivers */
+#endif
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
        u32 schmt:2;            /* schmitt enable            */
 #endif
@@ -159,6 +171,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
                                int len);
 
+struct pmux_pingrp_desc {
+       u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+       u8 ctl_id;
+       u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define PMUX_SLWF_MIN  0
@@ -208,14 +230,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 
 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 
-struct pmux_pingrp_desc {
-       u8 funcs[4];
-#if defined(CONFIG_TEGRA20)
-       u8 ctl_id;
-       u8 pull_id;
-#endif /* CONFIG_TEGRA20 */
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+struct pmux_mipipadctrlgrp_config {
+       u32 grp:16;     /* pin group PMUX_MIPIPADCTRLGRP_x   */
+       u32 func:8;     /* function to assign PMUX_FUNC_... */
 };
 
-extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+void pinmux_config_mipipadctrlgrp_table(
+       const struct pmux_mipipadctrlgrp_config *config, int len);
+
+struct pmux_mipipadctrlgrp_desc {
+       u8 funcs[2];
+};
+
+extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
 
 #endif /* _TEGRA_PINMUX_H_ */